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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? integrated single-chip 10/100/1000 ethernet switch ? eight 10/100 mbps auto-negotiating fast ethernet (fe) ports with rmii, mii, gpsi, reverse mii & reverse gpsi interface options ? one 10/100/1000 mbps auto-negotiating port with gmii & mii interface options, that can be used as a wan uplink or as a 9th port ? a 10/100 mbps fast ethernet (fe) cpu port with reverse mii interface option ? operates stand-alone or can be cascaded with a second zl50410 to reach 16 ports ? embedded 2 mbits (256 kbytes) internal memory ? supports up to 4 k byte frames ? l2 switching ? mac address self learning, up to 4 k mac addresses using internal table ? supports ip multicast with igmp snooping, up to 4 k ip multicast groups ? supports the following spanning standards - ieee 802.1d spanning tree - ieee 802.1w rapid spanning tree ? supports ethernet multicasting and broadcasting and flooding control ? vlan support ? supports port-based vlan and tagged-based vlan (ieee 802.1q), up to 4 k vlans ? supports both shared vlan learning (svl) and independent vlan learning (ivl) ? supports private vlan edge (protected ports) ? cpu access supports the following interface options: ? 8/16-bit parallel and serial+mii interface in managed mode ? serial interface in lightly managed mode, or in unmanaged mode with optional i 2 c eeprom interface ? failover features ? rapid link failure detection using hardware-generated heartbeat packets december 2004 ordering information ZL50410GDC208 pin lbga -40 c to +85 c zl50410 managed 8-port 10/100m + 1-port 10/100/1000m ethernet switch data sheet figure 1 - system block diagram 8-port 10/100m + 1g ethernet switch quad 10/100 phy quad 10/100 phy 10/100/ 1000 phy c p u eeprom i 2 c rmii / mii / gpsi gmii / mii 8/16-bit or serial mi i zl50410
zl50410 data sheet 2 zarlink semiconductor inc. ? link failover in less than 50 ms ? rate control (both ingress and egress) ? bandwidth rationing, bandwidth on demand, sla (service level agreement) ? smooth out traffic to uplink port ? ingress rate control - back pressure - flow control - wred (weighted random early discard) ? egress rate control ? down to 16 kbps rate control granularity ? per queue traffic shaper on uplink port ? packet filtering and port security ? static address filtering for source and/or destination mac ? static mac address not subject to aging ? secure mode freezes mac address learning (each port may independently use this mode) ? supports port authentication (ieee 802.1x) ? qos support ? supports ieee 802.1p/q quality of service with 2 transm ission priority queues (4 for uplink port), with strict priority and/or wfq service disciplines ? provides 2 levels of dropping precedence with wred mechanism ? user controls the wred thresholds. ? buffer management: per class and per port buffer reservations ? port-based priority: vlan priority in a tagged frame can be overwritten by the priority of port vlan id ? supports per-system option to enable flow contro l for best effort frames even on qos enabled ports ? classification based on: ? port based priority ? vlan priority field in vlan tagged frame ? ds/tos field in ip packet ? udp/tcp logical ports: 8 hard-wired and 8 prog rammable ports, including one programmable range ? the precedence of the above classifications is programmable ? supports ieee 802.3ad link aggregation ? up to 8 trunk groups, with up to 8 ports per group ? allows trunking of ports located on cascaded chip ? supports load sharing among trunk ports based on: - source port - source and/or destination mac address ? supports module hot swap on all ports ? mib statistics counters for all ports ? full duplex ethernet ieee 802.3x flow control ? backpressure flow control for half duplex ports ? hardware auto-negotiation through mii management interface (mdio) for ethernet ports ? built-in reset logic triggered by system malfunction ? built-in self test for internal sram ? ieee-1149.1 (jtag) test port zl50410 data sheet 3 zarlink semiconductor inc. description the zl50410 is a low density, low cost, high performance, non-blocking ethernet switch chip. a single chip provides 8 ports at 10/100 mbps, 1 uplink port at 10/100/1000 mbps, and a cpu interface for managed, lightly managed and unmanaged switch applications. the chip supports up to 4 k mac addresses and up to 4 k tagged-based virtual lans (vlans). it also supports the pr ivate vlan edge feature, allowing the ability to set up protected ports in a tagged-based vlan system. with strict priority and/or wfq transmission scheduling and wred dropping schemes, the zl50410 provides powerful qos functions for various multimedia and mission- critical applications. the ch ip provides 2 transmission priorities (4 priorities for uplink port) and 2 levels of dropping precedence. each pack et is assigned a transmission priority and dropping precedence based on the vlan priority field in a vlan tagged frame, or the ds/tos field, or the udp/tcp logical port fields in ip packets. the zl50410 recognizes a total of 16 udp/tcp logical ports, 8 hard-wired and 8 programmable (inc luding one programmable range). the zl50410 provides the ability to monitor a li nk, detect a simple link failure, and provide no tification of the failure to the cpu. the cpu can then failover that link to an alternate link. the zl50410 supports up to 8 groups of port trunking/load sharing. each group can contain up to 8 ports. port trunking/load sharing can be used to group ports between in terlinked switches to increase the effective network bandwidth. in half-duplex mode, all ports support backpressure flow c ontrol, to minimize the risk of losing data during long activity bursts. in full-duplex mode, ieee 802.3x flow control is provided. the zl50410 also supports a per-system option to enable flow control for best effort frames, even on qos-enabled ports. statistical information for snmp and the remote moni toring management information base (rmon mib) are collected independently for all ports. access to these stat istical counters/registers is provided via the cpu interface. snmp management frames can be received and transmitted via the cpu interface, cr eating a complete network management solution. the zl50410 is fabricated using 0.18 micron technology. the zl50410 is packaged in a 208-pin ball grid array package. zl50410 data sheet table of contents 4 zarlink semiconductor inc. 1.0 bga and ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 bga views (top-view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 power and ground distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 ball signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.4 signal mapping and internal pull-up/down configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.5 bootstrap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5.1 recommended default boostrap settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.6 default switch configuration and initia lization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.1 internal memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 mac modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1 rmii mac module (rmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.1.1 gpsi (7ws) interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.2 cpu mac module (cmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.3 mii mac module (mmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2.4 phy addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3 management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.5 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.6 heartbeat packet generation and response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.7 timeout reset monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.8 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.0 management and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1 register configuration, fr ame transmission, and frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.1 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.2 rx/tx of standard ethernet frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.1.3 control frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.0 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3 frame forwarding to and from cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.4 mac address filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5 protocol filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.6 logical port filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.7 quality of service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 zl50410 data sheet table of contents 5 zarlink semiconductor inc. 5.8 priority classification rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 port based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.1 fcb manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.2 rx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.3 rxdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.2.5 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.2.6 txdma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 two qos configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.1 strict priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.2 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 wred drop threshold management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7 flow control basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.7.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.7.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.8 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.9 failover backplane feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.0 traffic mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 mirroring features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 using port mirroring for loop back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.0 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.1 system clock (sclk) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 10.1.2 rmac reference clock (m_clk) speed requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.3 mmac reference clock (ref_clk) speed requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1.4 jtag test clock (tck) speed requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 10.2 clock generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.1 mdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.2 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2.3 ethernet interface clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.0 hardware statistics counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.1 hardware statistics counters list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.2 ieee 802.3 hub management (rfc 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.1 readableoctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11.2.1.2 readableframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.3 fcserrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.4 alignmenterrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 zl50410 data sheet table of contents 6 zarlink semiconductor inc. 11.2.1.5 frametoolongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11.2.1.6 shortevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.7 runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.8 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.9 lateevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.10 verylongevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.11 dataratemisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.12 autopartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.2.1.13 totalerrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 ieee 802.1 bridge management (rfc 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.1 inframes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.2 outframes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.3 indiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.4 delayexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3.1.5 mtuexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4 rmon ? ethernet statistic group (rfc 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.1 drop events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.2 octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.4.1.3 broadcastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.4 multicastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.5 crcalignerrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.6 undersizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.7 oversizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4.1.8 fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4.1.9 jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4.1.10 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4.1.11 packet count for different size groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.5 miscellaneous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.1 zl50400 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2 directly accessed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.1 index_reg0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.2 data_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.3 control_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.4 command&status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.2.5 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2.6 control command frame buffer1 access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.2.7 control command frame buffer2 access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.3 indirectly accessed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.1 (group 0 address) mac ports group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.3.1.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 12.3.1.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 12.3.1.3 ecr3pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 12.3.1.4 ecr4pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 12.3.1.5 buf_limit ? frame buffer limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 12.3.1.6 fcc ? flow control grant period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 12.3.2 (group 1 address) vlan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.1 avtcl ? vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.2 avtch ? vlan type code register high. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.3 pvmap00_0 ? port 0 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 zl50410 data sheet table of contents 7 zarlink semiconductor inc. 12.3.2.4 pvmap00_1 ? port 0 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.5 pvmap00_3 ? port 0 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.3.2.6 pvmapnn_0,1,3 ? ports 1~9 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.2.7 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3.3 (group 2 address) port trunking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 12.3.3.1 trunkn? trunk group 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 12.3.3.2 trunkn_hash10 ? trunk group n hash result 1/0 destination port number . . . . . . . . . . . 74 12.3.3.3 trunkn_hash32 ? trunk group n hash result 3/2 destination port number . . . . . . . . . . . 74 12.3.3.4 trunkn_hash54 ? trunk group n hash result 5/4 destination port number . . . . . . . . . . . 75 12.3.3.5 trunkn_hash76 ? trunk group n hash result 7/6 destination port number . . . . . . . . . . . 75 multicast hash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.3.3.6 multicast_hashn-0 ? multicast hash result 0~7 ma sk byte 0 . . . . . . . . . . . . . . . . . . . . 76 12.3.3.7 multicast_hashn-1 ? multicast hash result 0~7 ma sk byte 1 . . . . . . . . . . . . . . . . . . . . 76 12.3.4 (group 3 address) cpu port configuration group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.3.4.1 mac0 ? cpu mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 12.3.4.2 mac1 ? cpu mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.3 mac2 ? cpu mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.4 mac3 ? cpu mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.5 mac4 ? cpu mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.6 mac5 ? cpu mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.7 int_mask0 ? interrupt mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 12.3.4.8 intp_mask0 ? interrupt mask for mac port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.9 intp_maskn ? interrupt mask fo r mac ports 2~9 registers . . . . . . . . . . . . . . . . . . . . . . . 78 12.3.4.10 rqs ? receive queue select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 12.3.4.11 rqss ? receive queue status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 12.3.4.12 mac01 ? increment mac port 0,1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.4.13 mac23 ? increment mac port 2,3 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12.3.4.14 mac45 ? increment mac port 4,5 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.15 mac67 ? increment mac port 6,7 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.16 mac9 ? increment mac port 9 address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.17 cpuqins0 - cpuqins6 ? cpu queue insertion co mmand . . . . . . . . . . . . . . . . . . . . . . 80 12.3.4.18 cpuqinsrpt ? cpu queue insertion report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.19 cpugrnhdl0 - cpugrnhdl1 ? cpu allocated granule pointer . . . . . . . . . . . . . . . . . 81 12.3.4.20 cpurlsinfo0 - cpurlsinfo4 ? receive queue stat us . . . . . . . . . . . . . . . . . . . . . . . 81 12.3.4.21 cpugrnctr ? cpu granule control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.5 (group 4 address) search engine group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.5.1 agetime_low ? mac address aging time low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.5.2 agetime_high ?mac address aging time high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.5.3 se_opmode ? search engine operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.3.6 (group 5 address) buffer control/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.6.1 qosc ? qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 12.3.6.2 ucc ? unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.6.3 mcc ? multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 12.3.6.4 mccth ? multicast threshold control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 12.3.6.5 rdrc0 ? wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 12.3.6.6 rdrc1 ? wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 12.3.6.7 rdrc2 ? wred rate control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 12.3.6.8 sfcb ? share fcb size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.9 c1rs ? class 1 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 12.3.6.10 c2rs ? class 2 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 12.3.6.11 c3rs ? class 3 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 12.3.6.12 avpml ? vlan tag priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 zl50410 data sheet table of contents 8 zarlink semiconductor inc. 12.3.6.13 avpmm ? vlan priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 12.3.6.14 avpmh ? vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 12.3.6.15 avdm ? vlan discard map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 12.3.6.16 tospml ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 12.3.6.17 tospmm ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 12.3.6.18 tospmh ? tos priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 12.3.6.19 tosdml ? tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 12.3.6.20 user_protocol_n ? user define protocol 0~7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12.3.6.21 user_protocol_force_discard ? user define protocol 0~7 force discard . . . . 89 user defined logical ports and well known ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.3.6.22 well_known_port[1:0]_priority- well known logic port 1 and 0 priority . . . . . . 90 12.3.6.23 well_known_port[3:2]_priority- well known logic port 3 and 2 priority . . . . . . 90 12.3.6.24 well_known_port[5:4]_priority- well known logic port 5 and 4 priority . . . . . . 90 12.3.6.25 well_known_port[7:6]_priority- well known logic port 7 and 6 priority . . . . . . 90 12.3.6.26 well_known_port_enable ? well known logic port 0 to 7 enables . . . . . . . . . . . 91 12.3.6.27 well_known_port_force_discard ? we ll known logic port 0~7 force discard91 12.3.6.28 user_port[7:0]_[lowithhigh] ? user define logi cal port 0~7 . . . . . . . . . . . . . . . . . . 92 12.3.6.29 user_port_[1:0]_priority - user define l ogic port 1 and 0 priority . . . . . . . . . . . . . 92 12.3.6.30 user_port_[3:2]_priority - user define l ogic port 3 and 2 priority . . . . . . . . . . . . . 92 12.3.6.31 user_port_[5:4]_priority - user define l ogic port 5 and 4 priority . . . . . . . . . . . . . 92 12.3.6.32 user_port_[7:6]_priority - user define l ogic port 7 and 6 priority . . . . . . . . . . . . . 93 12.3.6.33 user_port_enable[7:0] ? user define logic po rt 0 to 7 enables . . . . . . . . . . . . . . . 93 12.3.6.34 user_port_force_discard[ 7:0] ? user define logic port 0~7 force discard . . . . 93 12.3.6.35 rlowl ? user define range low bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.6.36 rlowh ? user define range low bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.6.37 rhighl ? user define range high bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.6.38 rhighh ? user define range high bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.6.39 rpriority ? user define range priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 12.3.7 (group 6 address) misc group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.3.7.1 mii_op0 ? mii register option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.3.7.2 mii_op1 ? mii register option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.3.7.3 fen ? feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 12.3.7.4 miic0 ? mii command register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.7.5 miic1 ? mii command register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 12.3.7.6 miic2 ? mii command register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.7 miic3 ? mii command register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.8 miid0 ? mii data register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.9 miid1 ? mii data register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 12.3.7.10 usd ? one micro second divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 12.3.7.11 device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3.7.12 checksum - eeprom checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.3.7.13 lhbtimer ? link heart beat timeout timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.14 lhbreg0, lhbreg1 - link heart beat opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.15 fmaccreg0, fmaccreg1 - mac control frame opcode . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3.7.16 fcb base address register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.7.17 fcb base address register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.7.18 fcb base address register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 12.3.8 (group 7 address) port mirroring group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.1 mirror control ? port mirror control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.2 mirror_dest_mac[5:0] ? mirror destination mac address 0~5 . . . . . . . . . . . . . . . . . 100 12.3.8.3 mirror_src _mac[5:0] ? mirror source mac address 0~5 . . . . . . . . . . . . . . . . . . . . . 100 12.3.8.4 rmac_mirror0 ? rmac mirror 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 zl50410 data sheet table of contents 9 zarlink semiconductor inc. 12.3.8.5 rmac_mirror1 ? rmac mirror 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.9 (group 8 address) per port qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.9.1 fcrn ? port 0~9 flooding control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.9.2 bmrcn - port 0~9 broadc ast/multicast rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.3.9.3 pr100_n ? port 0~7 reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 12.3.9.4 pr100_cpu ? port cpu reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.9.5 prm ? port mmac reservation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 12.3.9.6 pth100_n ? port 0~7 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02 12.3.9.7 pth100_cpu ? port cpu threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.9.8 pthg ? port mmac threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 12.3.9.9 qosc00, qosc01 - classes byte limit port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3.9.10 qosc02, qosc15 - classes byte limit port 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.11 qosc16 - qosc21 - classes byte limit cpu port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.12 qosc22 - qosc27 - classes byte limit mmac port . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.13 qosc28 - qosc31 - classes wfq credit for mmac. . . . . . . . . . . . . . . . . . . . . . . . . . 103 12.3.9.14 qosc36 - qosc39 - shaper control port mmac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.10 (group e address) system diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.10.1 dtsrl ? test output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 12.3.10.2 dtsrm ? test output selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 12.3.10.3 testout0, testout1 ? testmux output [7:0], [1 5:8] . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.10.4 mask0-mask4 ? timeout reset mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 12.3.10.5 bootstrap0 ? bootstrap3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.10.6 prtfsmst0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 12.3.10.7 prtqosst0-prtqosst7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.10.8 prtqosst8a, prtqosst8b (cpu port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12.3.10.9 prtqosst9a, prtqosst9b (mmac port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.10 classqosst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.3.10.11 prtintctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.12 qmctrl0~9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.13 qctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 12.3.10.14 bmbistr0, bmbistr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.10.15 bmcontrol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.10.16 buff_rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.3.10.17 fcb_head_ptr0, fcb_head_ptr1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.18 fcb_tail_ptr0, fcb_tail_ptr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.19 fcb_num0, fcb_num1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3.10.20 bm_rlsff_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.10.21 bm_rslff_info[5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.3.11 (group f address) cpu access group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.11.1 gcr - global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.3.11.2 dcr - device status and signature r egister. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.11.3 dcr1 - device status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 13 12.3.11.4 dpst ? device port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3.11.5 dtst ? data read back register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.3.11.6 da ? dead or alive register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 13.0 characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 13.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 13.4 ac characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.1 typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4.2 reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 zl50410 data sheet table of contents 10 zarlink semiconductor inc. 13.4.3 media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.4.4 general purpose serial interface (7-wire) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.4.5 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.4.6 i2c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.4.7 serial interface setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.4.8 jtag (ieee 1149.1-2001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 14.0 document history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.1 july 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.2 november 2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.3 february 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.4 august 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 14.5 november 2004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 zl50410 data sheet 11 zarlink semiconductor inc. 1.0 bga and ball signal descriptions 1.1 bga views (top-view) 1.2 power and ground distribution 12345678910111213141516 a sclk p_cs# p_rd# p_we # p_dat a1 p_dat a3 p_dat a5 p_dat a7 p_dat a9 p_dat a11 p_dat a13 p_dat a15 gref_ clk m9_tx clk m9_m txclk m9_tx en a bp_int # p_a0 p_a1 p_a2 p_dat a0 p_dat a2 p_dat a4 p_dat a6 p_dat a8 p_dat a10 p_dat a12 p_dat a14 tck tms m9_tx er m9_rx ck b c reset out# tsto ut1 tsto ut3 tsto ut5 tsto ut6 tsto ut7 tsto ut9 tsto ut11 tsto ut12 tsto ut14 tsto ut15 trst# tdi m9_rx d7 m9_c rs m9_c ol c dresin # tsto ut0 tsto ut2 tsto ut4 3.3v scan_ en tsto ut8 tsto ut10 1.8v tsto ut13 tdo 3.3v m9_rx d5 m9_rx d6 m9_rx dv m9_rx er d em2_c ol m0_c ol m1_c ol 3.3v 3.3v m9_rx d4 m9_tx d6 m9_tx d7 e fm_md c m_mdi o m0_rx d2 m0_rx d3 m9_rx d2 m9_rx d3 m9_tx d4 m9_tx d5 f gm0_rx d0 m0_rx d1 m0_rx ck m0_tx d3 gnd gnd gnd gnd m9_rx d0 m9_rx d1 m9_tx d2 m9_tx d3 g hm0_c rs m0_tx en m0_tx d2 1.8v gnd gnd gnd gnd 1.8v m7_c ol m9_tx d0 m9_tx d1 h jm0_tx d0 m0_tx d1 m0_tx ck m1_rx d3 gnd gnd gnd gnd m7_tx d3 m7_tx ck m7_tx d1 m7_tx d0 j km1_rx d0 m1_rx d1 m1_rx d2 m1_rx ck gnd gnd gnd gnd m7_tx d2 m7_rx d2 m7_tx en m7_c rs k lm1_c rs m1_tx en m1_tx d2 m1_tx d3 m7_rx d3 m7_rx ck m7_rx d1 m7_rx d0 l mm1_tx d0 m1_tx d1 m1_tx ck 3.3v 3.3v m6_c ol m5_c ol m4_c ol m nm2_rx d3 m2_tx ck m2_tx d3 m3_rx d3 3.3v m3_tx d3 1.8v m4_rx d3 m4_tx ck m4_tx d3 m5_rx d3 m5_tx ck m5_tx d3 m6_rx d3 m6_tx ck m6_tx d3 n pm2_rx d2 m2_rx ck m2_tx d2 m3_rx d2 m3_rx ck m3_tx d2 m3_c ol m4_rx d2 m4_rx ck m4_tx d2 m5_rx d2 m5_rx ck m5_tx d2 m6_rx d2 m6_rx ck m6_tx d2 p rm2_rx d1 m2_tx en m2_tx d1 m3_rx d1 m3_tx en m3_tx d1 m_clk m4_rx d1 m4_tx en m4_tx d1 m5_rx d1 m5_tx en m5_tx d1 m6_rx d1 m6_tx en m6_tx d1 r tm2_rx d0 m2_c rs m2_tx d0 m3_rx d0 m3_c rs m3_tx d0 m3_tx ck m4_rx d0 m4_c rs m4_tx d0 m5_rx d0 m5_c rs m5_tx d0 m6_rx d0 m6_c rs m6_tx d0 t 12345678910111213141516 g7-10, h7-10, j7-10, k7-10 gnd v ss ground d5, d12, e4, e13, m4, m13, n5 3.3v v cc i/o power d9, h4, h13, n7 1.8v v dd core power zl50410 data sheet 12 zarlink semiconductor inc. 1.3 ball signal descriptions all pins are cmos type; all input pins are 5 volt tolerance; and all output pins are 3.3 cmos drive. notes # = active low signal input = input signal input-st = input signal with schmitt-trigger output = output signal (tri-state driver) i/o-ts = input & output signal with tri-state driver pull-up = weak internal pull-up (nominal 100k ohm) (refer to section 1.4 on page 17 as some internal pull-ups are not enabled in certain configurations) pull-down = weak internal pull-down (nominal 100k ohm) (refer to section 1.4 on page 17 as some internal pull-downs are not enabled in certain configurations) ball signal description table ball no(s) symbol i/o description 16-bit cpu bus interface a12, b12, a11, b11, a10, b10, a9, b9, a8, b8, a7, b7, a6, b6, a5, b5 p_data[15:0] i/o-ts with pull-up processor bus data bit [15:0]. p_data[7:0] is used in 8-bit mode. b4, b3, b2 p_a[2:0] input with pull-up processor bus address bit [2:0] a4 p_we# input with pull-up cpu bus-write enable a3 p_rd# input cpu bus-read enable a2 p_cs# input with pull-up chip select b1 p_int# output cpu interrupt fast ethernet access ports [7:0] mii l13, k14, l15, l16, n14, p14, r14, t14, n11, p11, r11, t11, n8, p8, r8, t8, n4, p4, r4, t4, n1, p1, r1, t1, j4, k3, k2, k1, f4, f3, g2, g1 m[ 7 :0]_rxd[3:0] input with pull-up ports [ 7 :0] ? receive data bit [3:0] k16, t15, t12, t9, t5, t2, l1, h1 m[ 7 :0]_crs_dv input with pull-up ports [ 7 :0] ? carrier sense and receive data valid zl50410 data sheet 13 zarlink semiconductor inc. k15, r15, r12, r9, r5, r2, l2, h2 m[ 7 :0]_txen output, slew ports [ 7 :0] ? transmit enable this pin also serves as a bootstrap pin. j13, k13, j15, j16, n16, p16, r16, t16, n13, p13, r13, t13, n10, p10, r10, t10, n6, p6, r6, t6, n3, p3, r3, t3, l4, l3, m2, m1, g4, h3, j2, j1 m[ 7 :0]_txd[3:0] output, slew ports [ 7 :0] ? transmit data bit [3:0] h14, m14, m15, m16, p7, e1, e3, e2 m[ 7 :0]_col input with pull-down ports[ 7 :0] ? collision j14, n15, n12, n9, t7, n2, m3, j3 m[ 7 :0]_txclk input or output with pull-up ports[ 7 :0] ? transmit clock this pin in an output if ecr4pn[0]='1' l14, p15, p12, p9, p5, p2, k4, g3 m[ 7 :0]_rxclk input or output with pull-up ports[ 7 :0] ? receive clock this pin in an output if ecr4pn[1]='1' gigabit ethernet uplink port gmii e16, e15, f16, f15, g16, g15, h16, h15 m9_txd[7:0] output transmit data bit [7:0] d15 m9_rxdv input with pull-up receive data valid d16 m9_rxer input with pull-up receive error c15 m9_crs input with pull-down carrier sense c16 m9_col input with pull-down collision detected b16 m9_rxclk input or output with pull-up receive clock in mii mode, this pin in an output if ecr4p9[1]='1' c14, d14, d13, e14, f14, f13, g14, g13 m9_rxd[7:0] input with pull-up receive data bit [7:0] a16 m9_txen output with pull-up transmit data enable this pin also serves as a bootstrap pin. b15 m9_txer output with pull-up transmit error this pin also serves as a bootstrap pin. ball signal description table (continued) ball no(s) symbol i/o description zl50410 data sheet 14 zarlink semiconductor inc. a15 m9_mtxclk input with pull-up transmit clock a14 m9_txclk output gigabit transmit clock test interface c11, c10, d10, c9, c8, d8, c7, d7, c6, c5, c4, d4, c3, d3, c2, d2 tstout[15:0] output [15:4] reserved [3] eeprom checksum is good [2] initialization completed [1] memory self test in progress [0] initialization started these pins also serve as bootstrap pins. test facility c13 tdi input with pull-up jtag - test data in c12 trst# input with pull-up jtag - test reset b13 tck input with pull-up jtag - test clock b14 tms input with pull-up jtag - test mode state d11 tdo output jtag - test data out d6 scan_en input must be externally pulled-down scan enable. manufacturing test option. should be externally pulled-down for proper operation. system clock, power, and ground pins a1 sclk input system clock. based on system requirement, sclk needs to operate at difference frequency. sclk requires 40/60% duty cycle clock. d9, h4, h13, n7, v dd power +1.8 volt dc supply d5, d12, e4, e13, m4, m13, n5, v cc power +3.3 volt dc supply g7-10, h7-10, j7-10, k7-10 v ss power ground ground misc. d1 resin# input reset input c1 resetout# output reset phy ball signal description table (continued) ball no(s) symbol i/o description zl50410 data sheet 15 zarlink semiconductor inc. f1 m_mdc output mii management data clock f2 m_mdio i/o-ts with pull-up mii management data i/o r7 m_clk input rmac reference clock a13 gref_clk input with pull-up gmac reference clock bootstrap pins (1= pull-up 0= pull-down) 1 (see ?bootstrap options? on page 20) d2 tstout[0] input (reset only) enable debounce of strobe signal pullup ? enabled pulldown - disabled c3, d3, c2 tstout[3:1] input (reset only) management interface operation mode: 000 ? 16-bit parallel interface 001 ? 8-bit parallel interface 010 ? serial with mii as ethernet frame transfer interface. 011 ? serial only. cpu can transmit/receive frames with the serial interface. 111 ? unmanaged serial. no cpu packet can be transmit or received with the serial interface. eeprom can be used to configure the device at bootup. a one (1) indicates pullup. a zero (0) indicates pulldown. tstout[1] is the least significant bit (lsb). c5, c4, d4 tstout[6:4] input (reset only) device id. default address of the device for serial interface. up to 8 device can be sharing the serial management bus with different device id. a one (1) indicates pullup. a zero (0) indicates pulldown. tstout[4] is the least significant bit (lsb). c6 tstout[7] input (reset only) eeprom not installed. pullup: not installed pulldown: installed d7 tstout[8] input (reset only) must be externally pulled-up manufacturing option. must be pulled up. ball signal description table (continued) ball no(s) symbol i/o description zl50410 data sheet 16 zarlink semiconductor inc. c7 tstout[9] input (reset only) module detect pullup: enable. in this mode, the device will detect the existence of a phy (for hot swap purpose). pulldown: disable d8 tstout[10] input (reset only) must be externally pulled-down manufacturing option. must be pulled down. c8 tstout[11] input (reset only) power saving pullup: enable mac power saving mode pulldown: disable mac power saving mode c9 tstout[12] input (reset only) timeout reset enable pullup: enable pulldown: disable c11, c10, d10 tstout[15:13] input (reset only) must be externally pulled-up manufacturing options. must be pulled-up. k15, r15, r12, r9, r5, r2, l2, h2 m[7:0]_txen input (reset only) user defined bootstrap: usually used in conjuction with module detect to determine what interface to use for the inserted module. can be read from bootstrap2 register a16, b15 m9_txen, m9_txer input with pull-up (reset only) user defined bootstrap: usually used in conjuction with module detect to determine what interface to use for the inserted module. can be read from bootstrap3 register 1. external pull-up/down resistors are required on all bootstrap pins for proper operation. recommend 10k for pull-ups and 1k f or pull-downs. ball signal description table (continued) ball no(s) symbol i/o description zl50410 data sheet 17 zarlink semiconductor inc. 1.4 signal mapping and internal pull-up/down configuration the zl50410 fast ethernet access ports (0-7) support 3 interface options: rmii, mii & gpsi. the table below summarizes the interface signals required for each interf ace and how they relate back to the pin symbol name shown in the ?ball signal description table? on page 12. it also specifies whether the in ternal pull-up/down resistor is present for each pin in the specific operating mode. notes : i ? input o ? output u ? pullup d - pulldown fast ethernet access ports pin symbol no module (bootstrap tstout9=?1?) rmii mode (ecr4pn[4:3]='11') mii mode (ecr4pn[4:3]='01') gpsi mode (ecr4pn[4:3]='00') m[7:0]_rxd0 (u) m[7:0]_rxd0 (i) m[7:0]_rxd0 (i) m[7:0]_rxd (i) m[7:0]_rxd1 (u) m[7:0]_rxd1 (i) m[7:0]_rxd1 (i) nc (u) m[7:0]_rxd2 (u) nc (u) m[7:0]_rxd2 (i) nc (u) m[7:0]_rxd3 (u) nc (u) m[7:0]_rxd3 (i) nc (u) m[7:0]_txen (o) m[7:0]_txen (o) m[7:0]_txen (o) m[7:0]_txen (o) m[7:0]_crs_dv (u) m[7:0]_crs_dv (i) m[7:0]_dv (i) m[7:0]_crs (i) m[7:0]_txd0 (o) m[7:0]_txd0 (o) m[7:0]_txd0 (o) m[7:0]_txd (o) m[7:0]_txd1 (o) m[7:0]_txd1 (o) m[7:0]_txd1 (o) nc (o) m[7:0]_txd2 (o) nc (o) m[7:0]_txd2 (o) nc (o) m[7:0]_txd3 (o) nc (o) m[7:0]_txd3 (o) nc (o) m[7:0]_col (d) nc (d) m[7:0]_col (i) m[7:0]_col (i) m[7:0]_txclk (u) nc (u) m[7:0]_txclk (io) m[7:0]_txclk (io) m[7:0]_rxclk (u) nc (u) m[7:0]_rxclk (io) m[7:0]_rxclk (io) table 1 - signal mapping in different operation mode zl50410 data sheet 18 zarlink semiconductor inc. the zl50410 gigabit ethernet uplink por t (port 9) supports 2 interface options: gmii & mii. the table below summarizes the interface signals required for each interf ace, and how they relate back to the pin symbol name shown in ?ball signal description table? on page 12. gigabit ethernet uplink port pin symbol no module (bootstrap tstout9=?1?) gmii mode (ecr4p9[4:3]='11') mii mode (ecr4p9[4:3]='00') m9_rxd0 (u) m9_rxd0 (i) m9_rxd0 (i) m9_rxd1 (u) m9_rxd1 (i) m9_rxd1 (i) m9_rxd2 (u) m9_rxd2 (i) m9_rxd2 (i) m9_rxd3 (u) m9_rxd3 (i) m9_rxd3 (i) m9_rxd4 (u) m9_rxd4 (i) nc (u) m9_rxd5 (u) m9_rxd5 (i) nc (u) m9_rxd6 (u) m9_rxd6 (i) nc (u) m9_rxd7 (u) m9_rxd7 (i) nc (u) m9_rxdv (u) m9_rxdv (i) m9_rxdv (i) m9_rxer (u) m9_rxer (i) nc (u) m9_crs (d) m9_crs (i) m9_crs (i) m9_col (d) m9_col (i) m9_col (i) m9_rxclk (u) m9_rxclk (i) m9_rxclk (io) m9_txd0 (o) m9_txd0 (o) m9_txd0 (o) m9_txd1 (o) m9_txd1 (o) m9_txd1 (o) m9_txd2 (o) m9_txd2 (o) m9_txd2 (o) m9_txd3 (o) m9_txd3 (o) m9_txd3 (o) m9_txd4 (o) m9_txd4 (o) nc (o) m9_txd5 (o) m9_txd5 (o) nc (o) m9_txd6 (o) m9_txd6 (o) nc (o) m9_txd7 (o) m9_txd7 (o) nc (o) m9_txen (u) m9_txen (o) m9_txen (o) m9_txer (u) m9_txer (o) nc (o) m9_txclk (o) m9_txclk (o) nc (o) gref_clk (u) gref_clk (i) ref_clk (i) m9_mtxclk (u) m9_mtxclk (i) m9_mtxclk (i) table 2 - signal mapping in different operation mode zl50410 data sheet 19 zarlink semiconductor inc. the zl50410 cpu access support 5 interface options: 8 or 16 -bit parallel, serial+mii (port 8), serial only, and unmanaged serial (with optional eeprom). the table below summarizes the interface signals required for each interface, and how they relate back to the pin symbol name shown in ?ball signal description table? on page 12. management interface pin symbol 16-bit cpu (tstout[3:1]=?000?) 8-bit cpu (tstout[3:1]=?001?) serial with mii (tstout[3:1]=?010?) serial only (tstout[3:1]=?011? or ?111?) p_a[0] p_a[0] (i) p_a[0] (i) nc (u) sda (iou) (111 only) p_a[1] p_a[1] (i) p_a[1] (i) nc (u) scl (ou) (111 only) p_a[2] p_a[2] (i) p_a[2] (i) nc (u) nc (u) p_we# p_we# (i) p_we# (i) strobe (iu) strobe (iu) p_rd# p_rd# (i) p_rd# (i) dataout (o) dataout (o) p_cs# p_cs# (i) p_cs# (i) datain (iu) datain (iu) p_int# p_int# (o) p_int# (o) p_int# (o) p_int# (o) p_data0 p_data0 (iou) p_data0 (iou) cpu_mii_txd0 (o) nc (u) p_data1 p_data1 (iou) p_data1 (iou) cpu_mii_txd1 (o) nc (u) p_data2 p_data2 (iou) p_data2 (iou) cpu_mii_txd2 (o) nc (u) p_data3 p_data3 (iou) p_data3 (iou) cpu_mii_txd3 (o) nc (u) p_data4 p_data4 (iou) p_data4 (iou) cpu_mii_txclk (o) nc (u) p_data5 p_data5 (iou) p_data5 (iou) cpu_mii_txen (o) nc (u) p_data6 p_data6 (iou) p_data6 (iou) nc (u) nc (u) p_data7 p_data7 (iou) p_data7 (iou) nc (u) nc (u) p_data8 p_data8 (iou) nc (u) cpu_mii_rxd0 (i) nc (u) p_data9 p_data9 (iou) nc (u) cpu_mii_rxd1 (i) nc (u) p_data10 p_data10 (iou) nc (u) cpu_mii_rxd2 (i) nc (u) p_data11 p_data11 (iou) nc (u) cpu_mii_rxd3 (i) nc (u) p_data12 p_data12 (iou) nc (u) cpu_mii_rxclk (o) nc (u) p_data13 p_data13 (iou) nc (u) cpu_mii_rxdv (i) nc (u) p_data14 p_data14 (iou) nc (u) nc (u) nc (u) p_data15 p_data15 (iou) nc (u) nc (u) nc (u) table 3 - signal mapping in different operation mode zl50410 data sheet 20 zarlink semiconductor inc. 1.5 bootstrap options tstout[15:0], m[7:0]_txen, m9_txen and m9_txer pins serve as bootstrap pins during device power-up or reset. please refer to ?typical reset & bootstrap timing diagram? on page 124 for more information on when the bootstrap pins are sampled. the bootstrap pins requ ire external pull-up/down re sistors for pr oper operation. the table below summarizes the bootstrap options. 1.5.1 recommended default bootstrap settings the following are the recommended default settings for the bootstrap options: ? unmanaged/lightly managed ? reserved/manufacturing bootstraps - tstout[15:13,8] must be pulled-up - tstout[10] must be pulled-down ? cpu interface: - strobe debounce bootstrap, tstout[0], should be norma lly pulled-up, unless you wish to disable the debounce logic - cpu interface bootstrap, tstout[3:1], should be pulled-up to indicate unmanaged ssi cpu interface. to enable ssi-only lightly managed mode, pulled-down tstout[3]. to enable ssi+mii lightly managed mode, pulled-down tstout[3,1] feature description cpu interface the zl50410 allows the selection of 5 different management interfaces: 8/16-bit parallel, serial with mii, se rial only and unmanaged serial with i2c eeprom. tstout[3:1] is used to select the interface options mentioned above. if the serial interface is selected, additi on bootstrap options are required: ? tstout[0] enables or disables the debounce feature (refer to ?synchronous serial interface? on page 32) ? tstout[6:4] selects the device id also, in unmanaged mode, an optional i 2 c eeprom can be used to configure the device at power-up or reset. tstout[7] selects the eeprom option. ethernet interface the zl50410 supports module hotswap on all it's ports. this is enabled via tstout[9]. when enabled, bootstrap pins m[7:0]_txen (ports 0-7) and m9-txen & m9_txer (port 9) are used to specify the module type to support multiple ethernet interfaces during module hotswap. another feature is the mac power savings mode. when enabled via tstout[11], each port's ma c will detect inactivity on the port and go into a power savings state. when activity is detected once again on the port, the mac will come out of this state. misc. features one other feature selected via bootstrap is timeout reset enable (tstout[12]). this enables a monitoring block with the device which will detect if any hardware state machine is in a non-idle state for more than 5 seconds. refer to section 2.7 for more details on this feature. table 4 - bootstrap features zl50410 data sheet 21 zarlink semiconductor inc. - ssi device id bootstrap, tstout[6:4], should be pulled-down to indicate device id 0x0 for the ssi interface. can be changed to whatever device id required if more than one device on the ssi bus. - eeprom bootstrap, tstout[7], should be pulled-up to disable until the system is debugged. you can pull-down this bootstrap if using the optional eeprom in unmanaged mode (note: this bootstrap is not valid in any other cpu mode) ? module detect bootstrap, tstout[9], should be pulled-down - in lightly managed mode, you can enable the optional module detect feature - if enabled, need to use mn_txen to indicate module type ? power saving bootstrap, tstout[11], should be normally pulled-up ? timeout reset bootstrap, tstout[12], should be pull-down - once system is debugged, you can enable the optional feature with pull-up (refer to section 2.7 for more details on this feature) ? managed ? reserved/manufacturing bootstraps - tstout[15:13,6:4,8,7,0] must be pulled-up - tstout[10] must be pulled-down ? cpu interface - tstout[3:1], should be pulled-down to indicate 16-bit cpu mode - for 8-bit cpu mode, pull-up tstout[1] ? module detect bootstrap, tstout[9], should be pu lled-down, unless using the module detect feature - if enabled, need to use mn_txen to indicate module type ? power saving bootstrap, tstout[11], should be normally pulled-up ? timeout reset bootstrap, tstout[12], should be pull-down - once system is debugged, you can enable the optional feature with pull-up (refer to section 2.7 for more details on this feature) 1.6 default switch configur ation and initialization sequence the zl50410 will come out of reset in a default configuration, which w ill allow for basic l2 switching and automatic mac address learning. in unmanaged mode, the default configurat ion will take effect immediately after reset. the default settings can be changed using the optional eeprom. ?system defaults ? port-based vlan ? mac address 00-00-00-00-00-00 not learned ? drop mac addresses 01-80-c2-00-00-01~f ? no ip multicast switching support ? trunking and mirroring disabled ? mac address agetime is 300 seconds ? vlan 802.1p prioritization - all priority bits mapped to priority 0 (lowest) ? 96 queued unicast/multicast frames will trigger flow control ? all wred drop percentages equal to 0% ? unicast/multicast/broadcast flood control disabled ? no shared or per-class buffer pools ? per-port defaults ? disable per-port fixed priority and drop precedence ? disable asynchronous flow control ? spanning tree per-port state equal to forwarding ? don?t filter tagged/untagged vlan frames zl50410 data sheet 22 zarlink semiconductor inc. ? automatic learning enabled ? per-port security disabled ? support frame size 64 <= n <= 1522 ? pad transmit frames < 64b ? standard preamble ? strict priority scheduling ?fe ports - rmii mode - auto-negotiate 100m/ful l duplex/flow control - rate control disabled - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers ?uplink port - gmii mode - auto-negotiate 1000m/full duplex/flow control - per-source port buffer pool of 384 buffers, with flow control threshold of 192 buffers in lightly managed/managed mode, the def ault configuration can be used as well, however, the device needs to be told when to start switching. this is done via the ?init complete? bit, set in gcr[4]. the default settings can be overridden using the cpu interface, bu t should be done before setting of gcr[4]. one thing to note is after reset, the device will start to initialize t he control tables. therefore, a short delay (100us~1ms) is necessary before changing the register setti ngs and/or control tables, and before setting gcr[4]. ?system defaults ? cpu mac address is 00-00-00-00-00-00 ? forward mac addresses 01-80-c2-00-00-00~ff to cpu port - except 01-80-c2-00-00-01~f, which are dropped ? all interrupts enabled ? mac address learn report to cpu disabled ? statistics counters disabled ? diffserv ef code support disabled ? no vlan id hashing ? per-port defaults ?fe ports - link heart beat disabled ? cpu port - 100m/full duplex/flow control - 8-byte header padding - per-source port buffer pool of 96 buffers, with flow control threshold of 48 buffers zl50410 data sheet 23 zarlink semiconductor inc. 2.0 block functionality figure 2 - functional block diagram 2.1 internal memory two megabit of internal memory is provided for ethernet frame data buffering (fdb), storing of mac control table database (mct), and the network management (nm) database statistics c ounters and mib. the mct is used for storing mac addresses and their physical port number. the fdb is used for storing the received frame data contents. the content s are stored in this memory until it is ready to be transmitted to the egress port. a memory arbiter is used to arbitrary the memory access r equests from various sources. a built in self test (bist) is used to detect any error in the memory array when the device is powered up. the bist can also be requested by the writing to t he gcr register. 2.2 mac modules 2.2.1 rmii mac module (rmac) the rmii media access control (rmac) module provides the necessary buffers and control interface between the frame engine (fe) and the external phys ical device (phy). it has five interfaces: mii, rmii, gpsi (only for 10m), reverse mii, or reverse gpsi (only for 10m). the rmac of the zl50410 device meets the ieee 802.3 specif ication. it is able to operate in either half or full duplex mode with a back pressure/flow control mechanism . in addition, it will automatically retransmit upon collision for up to 16 total transmissions. these eight ports are denoted as ports 0 to 7. the ph y addresses for the phy devices connected to the 8 rmac ports has to be from 08h (port 0) to 0fh (port 7). internal memory frame engine gmac rmac x 8 search engine management module other internal memory block 8 g zl50410 data sheet 24 zarlink semiconductor inc. 2.2.1.1 gpsi (7ws) interface the rmac ethernet port can function in gpsi (7ws) mode. in this mode, the txd[0], rxd[0] serve as tx data, rx data and respectively. the link and duplex of the port can be controlled by programming the ecr1pn register. only port-based vlan is suppo rted with gpsi interface. 2.2.2 cpu mac module (cmac) the cpu media access control (cmac) module provides t he necessary buffers and control interface between the frame engine (fe) and the external cpu device. it support either a reverse mii interface, providing the necessary interface tx and rx clocks to the cpu, or a register access mechanism vi a the 8/16-bit or serial interface. using the mii interface, the cmac of the zl50410 device meets the ieee 8 02.3 specification. it is able to operate in either half or full duplex mode with a back pressure /flow control mechanism. in addition, it will automatically retransmit upon collision for up to 16 total transmissions. this port is denoted as port 8. 2.2.3 gmii mac module (gmac) the gmii media access control (gmac) module provides the necessary buffer s and control interface between the frame engine (fe) and the external physical device (phy ). the gmac implements both gmii and mii interface, which offers a simple migration from 10/100 to 1g. the gmac of the zl50410 device meets t he ieee 802.3z specification. it is able to operate in 10m/100m either half or full duplex mode with a back pressure/flow control mechanism or in 1g full duplex mode with flow control mechanism. furthermore, it will automatically retrans mit upon collision for up to 16 total transmissions. this port is denoted as port 9. the phy address for the phy device connected to the gmac port has to be 10h. 2.2.4 phy addresses the table below provides an overview of the phy addresses required for each po rt in order for the mdio auto-negotiation to work between the zl50410 mac and t he phy device. if a different phy address is used, then the port must be manually brought up and the phy will need to be polled for link status via the miic/d registers. 2.3 management module the cpu can send a control frame to access or conf igure the internal network management database. the management module decodes the control frame and executes the functions requested by the cpu. this module is only active in managed mode. in unman aged mode, no control frame is accepted by the device. mac port phy address rmac port 0 0x08 rmac port 1 0x09 ... ... rmac port 7 0x0f cmac port 8 na gmac port 9 0x10 table 5 - phy addresses zl50410 data sheet 25 zarlink semiconductor inc. 2.4 frame engine the main function of the frame engine is to forward a fr ame to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 by tes) and formulates a switching request, sent to the search engine, to resolve the destination port. the arriving frame is moved to the internal memo ry. after receiving a switch response from the search en gine, the frame engine per forms transmission scheduling based on the frame?s priority. the frame engine forwards the frame to t he mac module when the frame is ready to be sent. 2.5 search engine the search engine resolves the fram e?s destination port or ports accordi ng to the destination mac address (l2) or ip multicast address (ip multicast packet) by searching the database. it also perfor ms mac learning, priority assignment, and trunking functions. 2.6 heartbeat packet generation and response the zl50410 provides the ability to monitor a link and detect a simple link failure. the link heart beat (lhb) packet generation module allows simultaneous tracking of all the rmac ports. periodically, a lhb message will be s ent for each link when inactivity is detected with in a programmable time period, if a reply is not received in a specified amount of time, the failover detection module will identify a point-to-point failure for that link. the fail over detection module will then interrupt the cpu. the lhb packet response module can also reply to lhb messages initiated by other zl50410 devices in the system, or by non-zl50410 devices which use a conventional and recognizable lhb message format. 2.7 timeout reset monitor the zl50410 supports a state machine monitoring block whic h can trigger a reset or inte rrupt if any state machine is determined to be stuck in a non-idle state for more t han 5 seconds. this feature is enabled via a bootstrap pin (tstout12). it also requires some regist er configuration via the cpu interface. see programming timeout reset application note, zlan-41, for more information. 2.8 jtag an ieee1149.1 compliant test inte rface is provid ed for boundary scan. zl50410 data sheet 26 zarlink semiconductor inc. 3.0 management and configuration one extra port is dedicated to the cpu via the cpu interface module. three modes this port can operate: managed, lightly managed or unmanaged mode. the differen t between these modes is tx/rx ethernet frame, tx/rx control frame and receiving interrupt due to the lack of constant attention or processing power from the cpu. the cpu interface utilizes a 8/16-bit bus in managed mode. it also supports a serial+mii, serial only, and an i 2 c interface, which provides an easy and lower cost way to configure the system for reduced management. supported cpu interface modes are 1. 16-bit cpu interface similar to the industr y standard architecture (isa) specification. 2. 8-bit cpu interface similar to isa. 3. serial with mii. a synchronous seri al interface (ssi) bus is used for ac cessing the configur ation register and control frame. mii is used for sending and receiving cpu packets. 4. lightly managed serial. configuratio n registers access, control frame and cpu transmit/receive packets are sent through a synchronous serial interface (ssi) bus. 5. unmanaged serial. the device can be configured by eepr om using an i2c interface at bootup, or via a syn- chronous serial interface ( ssi) otherwise. all configurati on registers and internal control blocks are accessible by the interface. however, the cpu cannot receive or tr ansmit frames nor will it receive any interrupt informa- tion. the cpu interface provides for easy and effective management of the switching system. figure 3 on page 27 provides an overview of the 8/16-bit interface. figure 4 on page 28 provides an overview of the ssi interface. figure 5 on page 29 provi des an overview of the ssi+mii interface. operation mode isa interface serial mii i2c 16-bit cpu 16-bit na na na 8-bit cpu 8-bit na na na serial with mii interface na yes yes no lightly managed serial na yes no no unmanaged serial na yes no yes table 6 - supported cpu interface modes zl50410 data sheet 27 zarlink semiconductor inc. figure 3 - overview of the 8/16-bit interface cpu frame transmit fifo index reg 0 (addr = 0) index reg 1 (addr = 1) internal registers inderect access 16-bit address config data reg (addr = 2) 8-bit data bus cpu frame receive fifo cpu frame reg (addr = 3) 8/16-bit data bus control command 1 reg (addr = 6) control command 1 receive fifo interrupt control command 2 transmit fifo control command 1 transmit fifo command/ status reg (addr = 4) interrupt reg (addr = 5) control command 2 reg (addr = 7) 8/16-bit data bus i/o data mux 8/16-bit data bus address processor 3-bit address bus p_cs# p_rd# p_we# p_int# zl50410 data sheet 28 zarlink semiconductor inc. figure 4 - overview of the ssi interface cpu frame transmit fifo index reg 0 (addr = 0) index reg 1 (addr = 1) internal registers inderect access 16-bit address config data reg (addr = 2) 8-bit data bus cpu frame receive fifo cpu frame reg (addr = 3) 8/16-bit data bus control command 1 reg (addr = 6) control command 1 receive fifo interrupt control command 2 transmit fifo control command 1 transmit fifo command/ status reg (addr = 4) interrupt reg (addr = 5) control command 2 reg (addr = 7) 8/16-bit data bus i/o data mux address processor int cs w r synchronous serial interface 16-bit data bus 3-bit address bus strobe serial in serial out interrupt zl50410 data sheet 29 zarlink semiconductor inc. figure 5 - overview of the ssi+mii interface 3.1 register configuration, frame transmission, and frame reception 3.1.1 register configuration the zl50410 has many programmable parameters, covering su ch functions as qos weights, vlan control, and port mirroring setup. in managed mode, the cpu interfac e provides an easy way of configuring these parameters. the parameters are contained in 8-bit co nfiguration registers. the device allows indirect access to these registers, as follows: ? if operating in 8-bit interface mode, two ?index? regi sters (addresses 000b and 001b) need to be written, to indicate the desired 16-bit register address. in 16-bi t mode, only one register (address 000b) needs to be written for the desired 16-bit register address. ? in serial mode, the address, command and data are shift ed in serially. to access the configuration registers, only one ?index? register (addresses 000b) needs to be written with the configuration register address. the desired data can be written into or read from the ?data? register (address 010b). ? for example, if ?xx? is required to be written to register ?yy?, a write of ?yy? is required to write to address ?000b? (index register). then, a write of ?xx? is required to write to address ?010b? (data register). this completes the r egister write and register ?yy? will contain the value of ?xx?. ? to indirectly configure the register addressed by the index register(s ), a ?data? register (address 010b) must be written with the desired 8-bit data. ? the zl50410 s upports special register-write in serial and 16-bit mode. this allows cpu to write to two consecutive configuration registers in a single write operation. by writing to bit[14] of configuration cpu frame transmit fifo index reg 0 (addr = 0) index reg 1 (addr = 1) internal registers inderect access 16-bit address config data reg (addr = 2) 8-bit data bus cpu frame receive fifo 8/16-bit data bus control command 1 reg (addr = 6) control command 1 receive fifo interrupt control command 2 transmit fifo control command 1 transmit fifo command/ status reg (addr = 4) interrupt reg (addr = 5) control command 2 reg (addr = 7) 8/16-bit data bus i/o data mux address processor int cs w r synchronous serial interface 16-bit data bus 3-bit address bus strobe serial in serial out mii interface txd txen rxd rxdv tclk rclk interrupt zl50410 data sheet 30 zarlink semiconductor inc. register address, cpu can write 16-bit data to address 010b. lower 8 bit of data is for the address specified in index register and upper 8 bit of data is for the address + 1. in 8-bit mode, this special feature will be ignored. ? similarly, to read the value in the register addressed by the index register(s), the ?data? register can now simply be read. ? the zl50410 s upports an incremental read/write. if cpu require s to read or write to the configuration registers incrementally, cpu only has to write to index register once with the msb of configuration register address set and then cpu can continuously read ing or writing to ?data? register (010b). in summary, access to the many internal registers is carr ied out simply by directly accessing only two registers ? one register to indicate the index of the desired parameter, and one register to read or write a value. of course, because there is only one bus master, there can nev er be any conflict between reading and writing the configuration registers. 3.1.2 rx/tx of standard ethernet frames in serial mode with mii, the mii interface is used for cp u to transmit and receive ethernet frames. in 8/16-bit or serial only mode, the ethernet frame is transmitted and received through the cpu interface. there is no ability to send/receive ethernet frames in unmanaged mode. to transmit a frame from the cpu in 8/16-bit or serial only mode: ? the cpu writes to the ?data frame? register (addres s 011) with the frame size, destination port number, and frame status. after writing all the transmitting status by tes, it then writes the data it wants to transmit (minimum 64 bytes). ? the zl50410 forwards the ethernet frame to the desired destination port, no lo nger distinguishing the fact that the frame originated from the cpu. to receive a frame into the cpu in 8/16-bit or serial only mode: ? the cpu receives an interrupt when an ethernet frame is available to be received. ? frame information arrives first in the data frame r egister. this includes source port number, frame size, and vlan tag. ? the actual data follows the frame information. the cpu uses the frame size information to read the frame out. to transmit a frame from the cpu with mii interface: ? zl50410 acts as a phy to provide receive clock (rxclk) to cpu so the cpu will depend on this receive clock to send packets to zl50410 ? zl50410 has the ability to halt the receive clock if the receive fifo of zl50410 is overflow. transmitting from cpu to zl50410 will resume once the receive fifo of zl50410 is no longer overflow ? follow the standard ethernet transmission format. cpu assert receive data valid (rxdv) before transmitting data to zl50410 and de-assert rxdv after transmitting the last data to receive a frame into the cpu with mii interface: ? zl50410 acts as a phy to provide transmit clock (txclk) to cpu so the cpu will de pend on the transmit clock to receive packets from zl50410 ? zl50410 has the ability to halt the transmit clock if the transmit fifo of zl50410 is under-run. cpu will resume receiving packets from zl50410 once the transmit fifo of zl50410 is no lo nger under-run ? follow the standard ethernet transmission format. cpu will see transmit enable (txen) be asserted by zl50410 and cpu can start receiving data. cpu w ill stop receiving data once txen is de-asserted by zl50410. 15 14 13 12 0 11 12 bit register address reserved inc r/w sp w zl50410 data sheet 31 zarlink semiconductor inc. in summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the cpu is a simple process that uses one direct access r egister only. in serial mode with mi i interface, the cpu will be allowed to transmit and receive frames using standard ieee 802.3 ethernet transmission format. the details of sending an ethernet fram e via the cpu interface is described in the processor interface application note, zlan-26. 3.1.3 control frames in addition to standard ethernet frames described in the preceding section, the cpu is also called upon to handle special ?control frames,? generated by the zl50410 and sent to the cpu. these proprietary frames are related to such tasks as statistics collection, mac address learning , and aging, etc? all contro l frames are up to 40 bytes long. transmitting and receiving these frames is similar to transmitting and receiving ethernet frames, except that the register accessed is the ?control frame data? register (address 111). specifically, there are the following types of contro l frames generated by the cpu and sent to the zl50410: ? memory read request ? memory write request ? learn unicast mac address ? delete unicast mac address ? search unicast mac address ? learn ip multicast address ? delete ip multicast address ? search ip multicast address ? learn multicast mac address ? delete multicast mac address ? search multicast mac address note: memory read and write requests by the cpu may include all internal memories which include statistic counters, mac address control link tabl e and the 2mbit (256kb) memory block. in addition, the following types of control frames are generated by the zl50410 and sent to the cpu: ? interrupt cpu when statistics counter rolls over ? response to memory read request from cpu ? learn unicast mac address ? delete unicast mac address ? delete multicast mac address ? delete ip multicast address ? response to search unicast mac address request from cpu ? response to search ip multicast address request from cpu ? response to search multicast mac address request from cpu the format of the control frame is described in the processor interface application note, zlan-26. 3.2 i 2 c interface the i2c interface serves the function of configuring the zl50410 at boot time. the master is the zl50410, and the slave is the eeprom memory. the i2c interface uses two bus lines, a serial data line (sda ) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfer of informat ion from eeprom to the switch. data transfer is 8-bit serial and bidirectional, at 50 kbps. data transfer is perf ormed between master and slave ic using a request / acknowledgment style of protocol. the master ic generates the timing signals and terminates data transfer. figure 6 depicts the data transfer format. the slave address is the memory address of the eeprom. refer to ?zl50410 register description? on page 60 for i2c address for each register. zl50410 data sheet 32 zarlink semiconductor inc. figure 6 - data transfer format for i2c interface 3.2.1 start condition generated by the master (in our case, the zl50410). the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transit ion of the sda line. other than in the start condition (and stop condition), the data on the sda line must be st able during the high period of scl. the high or low state of sda can only ch ange when scl is low. in addition, when the i2c bus is free, both lines are high. 3.2.2 address the first byte after the start condition determines which sl ave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 3.2.3 data direction the eighth bit in the first byte after the start condit ion determines the direction (r/w) of the message. a master transmitter sets this bit to w; a ma ster receiver sets this bit to r. 3.2.4 acknowledgment like all clock pulses, the acknowledgm ent-related clock pulse is generated by the master. however, the transmitter releases the sda line (high) during th e acknowledgment clock pulse. furthermo re, the receiver must pull-down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, then the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte, then the slave transmitter must release the sda line to let the master generate the stop condition. 3.2.5 data after the first byte containing the addr ess, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb first. 3.2.6 stop condition generated by the master. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. 3.3 synchronous serial interface the synchronous serial interface (ssi) serves the function of configuring the zl50410 not at boot time but via a pc. the pc serves as master and the zl50410 serves as slave. the protocol for the synchronous serial interface is nearly identical to the i2c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. debounce logic on th e clock signal (strobe) can be turned off to speedup command time. 3 id bits are used to allow up to eight zl50410 devices to share the same synchronous serial interface. the id of each device can be setup by bootstrap. to reduce the number of signals requ ired, the register address, command and data are shifted in serially through the datain pin. strobe- pin is used as the shift clock. dataout pin is used as data return path. start slave address r/w ack data 1 (8bits) ack data 2 ack data m ack stop zl50410 data sheet 33 zarlink semiconductor inc. each command consists of four parts. ?start pulse ? register address ? read or write command ? data to be written or read back write operation can be aborted in t he middle by sending an abort pulse to the zl50410. read operation can only be aborted before issuing the read command to the zl50410. a start command is detected when datain is sampled high when strobe- rise and datain is sampled low when strobe- fall. an abort command is detected when datain is sampled low when strobe- rise and datain is sampled high when strobe- fall. 3.3.1 write command all registers in zl50410 can be modified through this synchr onous serial interface. once the data has been sent, two extra stobe clocks must be generated to indicate t he end of the write command. the datain line should be held high for these two pulses. figure 7 - serial interface write command functional timing 3.3.2 read command all registers in zl50410 can be read thr ough this synchronous serial interface. figure 8 - serial interface read command functional timing strobe- d0 a0 a2 a1 w d0 d1 d2 d3 d12 d13 d14 d15 start addr cmd data 2 extra clocks after last transfer ... id2 id1 id0 id datain d0 autofd- a0 a1 a2 r d0 d1 d2 d12 d13 d14 d15 start addr cmd data ... strobe- id2 id1 id0 id datain dataout zl50410 data sheet 34 zarlink semiconductor inc. 4.0 data forwarding protocol 4.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available, because of advance buffer reservations. the memory (sram) interface is a 64-bit bus, connected to internal memory block. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port?s ?turn?, the rxdma will move 8 bytes (or up to the end-of-frame) from the port?s associated rxfifo into memory (frame data buffer, or fdb). once an entire frame has been moved to the fdb, a nd a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search en gine places a switch response in the switch response queue of the frame engine when done. among other inform ation, the search engine will have resolved the destination port of the frame and will have determi ned that the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the de stination port that it has a frame to forward. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then th e txq manager links the frame?s fcb to the correct per-port-per-class txq. the switch re sponse will come with 8 classified results. the txq manager will map this result into the per-port-per-class queue. unicast txq?s are linked lists of transmission jobs, represented by their associated frames? fcb?s. there is one linked list fo r each transmission class for each port. there are 2 transmission classes for each of the 8 rmac ports, and 4 classes for the gmac and cpu ports ? a total of 24 unicast queues. the txq manager is responsible for scheduling transmiss ion among the queues representing different classes for a port. when the port control module determ ines that there is room in the ma c transmission fifo (txfifo) for another frame, it requests the handl e of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from t he per-class queues for that port, using a zarlink semiconductor scheduling algorithm. the transmission dma (txdma) is responsible for multiple xing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eof) from memory into the port?s associated txfifo. after reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 4.2 multicast data frame forwarding after receiving the switch response, the txq manager has to make the dropping decisi on. a global decision to drop can be made, based on global fdb utilization and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so, then the fram e is dropped at some destinati ons but not others, and the fcb is not released. if the frame is not dropped at a particular destination port, then the txq manager formats an entry in the multicast queue for that port and class. multicas t queues are physical queues (unlike the linked lists for unicast frames). there are 2 multicast queues for each of the 8 rmac po rts. there are 4 multicast queues for the gmac and cpu ports. the mapping from the classified result to the priority queue is the same as the unicast traffic. by default, for the rmac ports to map the 8 transmit priorities into 2 multicast queues, the 2 lsb are discarded. for the gmac and cpu ports, to map the 8 transmit priorities into 4 mu lticast queues, the lsb is discarded. the priority mapping can be modified through memory config uration command. the multicast queue t hat is in fifo format shares the zl50410 data sheet 35 zarlink semiconductor inc. space in the internal memory block. the size and st arting address can also be programmed through memory configuration command. during scheduling, the txq manager treat s the unicast queue and the multicas t queue of the same class as one logical queue. the older head of line of the two queues is forwarded first. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined. 4.3 frame forwarding to and from cpu frame forwarding from the cpu port to a regular transmission port is nearly the same as forwarding between transmission ports. the only difference is that the physica l destination port must be indicated in addition to the destination mac address. frame forwarding to the cpu port is nearly the same as forwarding to a regular transmission port. the only difference is in frame scheduling. instead of us ing the patent-pending zarlin k semiconductor scheduling algorithms, scheduling for the cpu port is simply based on stri ct priority. that is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. there are four output queues to the cpu and one receive queue. 5.0 search engine 5.1 search engine overview the zl50410 search engine is optimized for high throughpu t searching, with enhanced features to support: ? up to 4 k of unicast/multicast mac addresses and ip multicast mac addresses ? up to 4 k vlans ? private vlan edge (protected ports) support ? up to 8 groups of port trunking ? traffic classification into 2 (or 4 for gmac) transmission priorities, and 2 drop precedence levels ? packet filtering based on mac address, protocol or logical port number ?security ? up to 4 k ip multicast groups ? individual flooding, broadcast, multicast storm control ? mac address learning and aging 5.2 basic flow shortly after a frame enters the zl50410 and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search engine. the switch request consists of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the switch respons e queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and comp resses the useful informat ion from the 64-byte switch request. among the information extracte d are the source and destination mac addresses, the packet?s vlan id, and whether the frame is unicast or multicast or broadcast. requests are sent to the sram to locate the associated entries in the mct table. when all the information has been collected from the sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other than the first of each linked list are maintained internal to the chip. if the desired mac address is still not fo und, then the result is either lear ning (source mac address unknown) or flooding (destination mac address unknown). in addition, vlan information is used to select the correct set of destination ports for the frame (for multicast), or to verify that the frame?s destination port is associated with the vlan (for unicast). zl50410 data sheet 36 zarlink semiconductor inc. if the destination mac address belongs to a port trunk, th en the trunk number is retr ieved instead of the port number. but on which port of the trunk will the frame be tr ansmitted? this is easily computed using a hash of the source and destination mac addresses. when all the information is compiled, the switch respons e is generated, as stated earlier. the search engine also interacts with the cpu with regard to learning and aging. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and desti nation mac address (or destination ip address for ip multicast) searching. as we indicated earlier, if a match is not found, th en the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. in tag-based vlan mode, if the frame is unicast, and the fr ame's destination port is rec ognized as a member of the vlan, then the frame is forwarded to that port; otherwise , the frame is forwarded to all the members in the vlan domain. if the frame is multicast or broadcast, the frame is forwarded to all the members in the vlan. moreover, if port trunking is enabled, this block selects the destina tion port (among those in the trunk group). in private vlan edge (protected ports) mode, the private vlan doma in is used for final qualif ication at the egress port. in port based vlan mode, a bit map is used to determin e whether the frame should be forwarded to the outgoing port. the main difference in this mode is that the bit map is not dynamic. ports cannot enter and exit groups because of real-time learning made by a cpu. the mac search block is also responsible for updat ing the source mac address timestamp used for aging. 5.3.2 learning the learning module learns new mac addresses and per forms port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. when cpu reporting is enabled, learning and port change will be perform ed when the cpu request queue has room, and a ?learn mac address? message is sent to the cpu. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a pr ogrammable ?age out? time interval. as we indicated earlier, the search module updates the source mac addr ess timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from th e table, and a ?delete mac address? message is sent to inform the cpu. supported mac entry types are: dynamic, static, source filt er, destination filter, ip multicast, source and destination filter, secure and multicast mac address. only dynamic entries can be aged; all others are static. the mac entry type is stored in the ?status? field of the mct data structure. 5.4 mac address filtering the zl50410's implementation of intelligent traffic swit ching provides filters for source and destination mac addresses. th is feature filters unnecessary traffic, thereby providing intelligent c ontrol over traf fic flows and broadcast traffic. broadcast, unknown unicast or unknown multicast mac ad dress and unknown ip multicast address can also be filter on per vlan basis. zl50410 data sheet 37 zarlink semiconductor inc. mac address filtering allows the zl50410 to block an incoming packet to an interface when it sees a specified mac address in either the source address or destination address of the incoming pa cket. for example, if your network is congested because of high utilization from a mac address, yo u can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem. 5.5 protocol filtering packet filtering can be performed bas ed on protocol type field in the pa ckets. up to eight protocols can be programmed to filter or allow packet to pass through the switch. 5.6 logical port filtering similar to protocol filtering, if the packet?s logical ports match the programma ble registers, the pa cket can be filtered or passed through the switch. up to eight pr ogrammable ports and one ranges can be assigned. 5.7 quality of service quality of service (qos) refers to the ability of a network to provide better service to selected network traffic over various technologies. primary goals of qos include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. traditional ethernet networks have had no prioritization of traffic. without a protocol to pr ioritize or differentiate traffic, a service level known as ?best effort? attempts to get all the packets to t heir intended destinations with minimum delay; however, there are no guarantees. in a congested network or when a low-performance switch/router is overloaded, ?best effort? becomes unsuita ble for delay-sensitive traffic and mission-critical data transmission. the advent of qos for packet-based systems accommo dates the integration of delay-sensitive video and multimedia traffic onto any existing ethern et network. it also alleviates the c ongestion issues that have previously plagued such ?best effort? networking systems. qos prov ides ethernet networks with the breakthrough technology to prioritize traffic and ensure that a certain transmission will have a guaranteed mini mum amount of bandwidth. extensive core qos mechanisms are built into the zl50410 architecture to ensure policy enforcement and buffering of the ingress port, as well as wei ghted fair-queue (wfq) scheduling at the egress port. in the zl50410, qos-based policies sort traffic into a sm all number of classes and mark the packets accordingly. the qos identifier provides specific treat ment to traffic in different classes, so that different quality of service is provided to each class. frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. for example, the overall se rvice given to frames and packets in the premium class will be better than that given to the st andard class; the premium class is expected to exper ience lower loss rate or delay. the zl50410 supports the following qos techniques: ? in a port-based setup, any station connected to the sa me physical port of the switch will have the same transmit priority. ? in a tag-based setup, a 3-bit field in the vlan tag prov ides the priority of the packet. this priority can be mapped to different queues in the switch to provide qos. ? in a tos/ds-based set up, tos stands for ?type of service? that may include ?minimize delay,? ?maximize throughput,? or ?maximize reliability.? network nodes ma y select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. ? in a logical port-based set up, a logical port provid es the application information of the packet. certain applications are more sensitive to delays than others; using logical ports to classify packets can help speed up delay sensitive applications, such as voip. zl50410 data sheet 38 zarlink semiconductor inc. 5.8 priority classification rule figure 9 shows the zl50410 pr iority classification rule. figure 9 - priority classification rule 5.9 port and tag based vlan the zl50410 supports two models fo r determining and controlling how a packet gets assigned to a vlan: port priority and tag -based vlan. 5.9.1 port-based vlan an administrator can use the pvmap registers to co nfigure the zl50410 for port-based vlan (see ?register definition? on page 60). for example, ports 1-3 might be assigned to the marketing vlan, ports 4-6 to the engineering vlan, and ports 7-9 to the administrative vlan. the zl50410 determines the vlan membership of each packet by noting the port on which it arrives. from there, the zl50410 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. yes n o n o n o n o yes yes yes yes n o n o use default port settings yes fix port priority? tos precedence over vlan? (qosc register bit 5) vlan tag? use vlan priority use t os use logical port use default port settings ip frame? ip frame? use logical port? zl50410 data sheet 39 zarlink semiconductor inc. for example, in the above table a 1 denot es that an outgoing port is eligible to receive a packet from an incoming port. a 0 (zero) denotes that an outgoing port is no t eligible to receive a packet from an incoming port. in this example: ? data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. ? data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. ? data packets received at port #2 are not eligible to be sent to ports 0 and 1. 5.9.2 tag-based vlan the zl50410 supports the ieee 802.1q s pecification for ?tagging? frames. th e specification defines a way to coordinate vlans across multiple switches. in the specif ication, an additional 4-octet h eader (or ?tag?) is inserted in a frame after the source mac address and before the frame ty pe. 12 bits of the tag are used to define the vlan id. packets are then switched through the network with each zl50410 simply swapping the incoming tag for an appropriate forwarding tag rather than processing each packet's contents to determine the path. this approach minimizes the processing needed once the packet enters the tag-switched network. in addition, coordinating vlan ids across multiple switches enables vlans to extend to multiple switches. up to 4 k vlans are supported in the zl50410. when tag- based vlan is enabled, each mac address is learned with it associated vlan. see ieee 802.1q vlan setup application note, zlan-51, for more information. 5.9.3 vlan stacking (q-in-q) the zl50410 partially supports vlan stacking, also call ed ieee 802.1q-in-q. this technology allows an additional vlan tag, called a provider vlan t ag, to be inserted into an existing i eee 802.1q tagged ethernet frame. this technology has been widely adapted in me tro ethernet applications since it prov ides a very cost-effective solution to transport multiple customers' vlan across the servic e provider's man/wan without interfering each other. the below figure illustrates the ieee 802.1q frame and the q-in-q frame, where th e provider vlan tag is inserted in front of the ieee 802.1q tag. destination port numbers bit map port registers 9 ? 2 1 0 register for port #0 pvmap00_0[7:0] to pvmap00_1[1:0] 0110 register for port #1 pvmap01_0[7:0] to pvmap01_1[1:0] 0101 register for port #2 pvmap02_0[7:0] to pvmap02_1[1:0] 0000 ? register for port #9 pvmap09_0[7:0] to pvmap09_1[1:0] 0000 table 7 - port-based vlan mapping zl50410 data sheet 40 zarlink semiconductor inc. figure 10 - q-in-q tagged ethernet frame the value of the tpid of the provider vlan tag is not assigned in the ieee 802.1ad standard. the zl50410 provides a global configurabl e tpid but only supports the extreme et hertype tpid (i.e. the stacked vlan tag cannot equal 0x81-00). see stacked vlan application note, zlan-82, for more information. 5.9.4 private vlan edge the pvlan edge (protected port) is a feature that has only local significance to the switch (unlike private vlans), and there is no isolation provided between two protected ports located on different l2 switches. a protected port does not forward any traffic (unicast, multicast, or broadcast) to any other port that is also a protected port in the same switch. traffic cannot be forwarded between protected por ts at l2, thus, all traffi c passing between protected ports must be forwarded through a layer 3 (l3) device. the zl50410 supports private vlan edge by allowing eac h of the rmac ports to se tup a private vlan domain, defined by registers pvlan_pn. the private vlan domain is used for final qualification at the egress port. see private vlan edge application not e, zlan-130, for more information. 5.10 ip mu lticast switching the zl50410 supports ip multicast filtering by: ? passively snooping on the igmp query and igmp report packets transferred between ip multicast routers and ip multicast host groups to learn ip multicast group members, and ? actively sending igmp query messages to solicit ip multicast group members. the purpose of ip multicast filtering is to optimize a swit ched network performance, so multicast packets will only be forwarded to those ports containing multicast group hosts members and routers instead of flooding to all ports in the subnet (vlan). the zl50410 with ip multicas t filtering/switching capab ility not only passively mo nitor igmp query and report messages, dvmrp probe messages, pim, and mospf hello messages; they also actively send igmp query messages to learn locations of multicast routers and member hosts in multicast groups within each vlan. see ip multicast switching application note, zlan-52, for more information. ieee 802.1q tagged ethernet frame dest mac (6 bytes) source mac (6 bytes) type/length (2 byte) data vlan tag protocol id (0x8100) vlan tci (2 bytes) provider tag (p-vlan) ieee 802.1q tag type/length (2 byte) data vlan tag protocol id (0x8100) vlan tci (2 bytes) dest mac (6 bytes) source mac (6 bytes) vlan tag protocol id (0x88a8*) vlan tci (2 bytes) ieee 802.1q tag ieee 802.1q-in-q tagged ethernet frame ieee 802.1q tag tpid = 0x8100 * provider tag tpid = configurable on per device basis zl50410 data sheet 41 zarlink semiconductor inc. 6.0 frame engine 6.1 data forwarding summary when a frame enters the dev ice at the rxmac, the rxdma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granu les in conjunction with the scheme for the sram interface. a switch request is sent to the search engine. the search engine processes the switch request. a switch response is sent back to the frame engine and indi cates whether the frame is unicast or multicast, and its destination port or ports. on receiving the response, the frame engine will check all the qos related information and decide if this frame can be forwarded. a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues. there are 2 txsch q for each rmac port (and 4 per gmac and cpu ports), one for each priority. creation of a queue entry either involves linking a new job to the appropr iate linked list if unicast, or adding an entry to a physi cal queue if multicast. when the port is ready to accept th e next frame, the txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling algor ithm (so as to ensure per-class quality of service). (the unicast linked list and the multicast queue for the same port-class pair are treat ed as one logical queue. the older hol between the two queues goes first. the txdma will pull frame data from the memory and fo rward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly descr ibes the functions of each of the modules of the zl50410 frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming fr ames, and releases fcb ha ndles upon frame departure. the fcb manager is also responsible for enforcing buffer re servations and limits that will be used for qos control and source port flow control. the default values can be determined by referring to section 7.6 on page 45. the frame buffer is managed in a 128bytes block unit. during initia lization, this block will link all the available blocks in a free buffer list. when each port is ready to receive, th is module hands the buffer handle to each requesting port. the fcb manager will also link the released buffer back into the free buffer list. the maximum buffer size can be increased from the standar d 1518 bytes (1522 with vlan tag) to up to 4 k bytes. this is done using buf_limit, and is enabled on a per port basis via bit [1 ] in ecr3pn. see buffer allocation application note, zlan-47, for more information. 6.2.2 rx interface the rx interface is mainly responsi ble for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. zl50410 data sheet 42 zarlink semiconductor inc. 6.2.4 txq manager first, the txq manager checks the per-c lass queue status and global reserved resource situation, and using this information, makes the frame dropping decision after rece iving a switch response. the dropping decision includes the head-of-link blocking avoidance if t he source port is not flow control enabled. if the decision is not to drop, the txq manager links the unicast frame?s fcb to the corr ect per-port-per-class txq and updates the fcb information. if multicast, the txq manager writes to the multicast queue for that por t and class and also update the fcb information including the duplicate count for this multic ast frame. the txq manager c an also trigger source port flow control for the incoming frame?s source if that por t is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues repres enting different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. the detail of the qos decis ion guideline is described in chapter 5. 6.2.5 port control the port control module calculates the sram read address for the frame currentl y being transmitted. it also writes start of frame information and an end of frame flag to t he mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.2.6 txdma the txdma multiplexes data and address fr om port control, and ar bitrates among buffer release requests from the port control modules. 7.0 quality of service and flow control 7.1 model quality of service is an all-encompassing term for which di fferent people have different interpretations. in general, the approach to quality of service descr ibed here assumes that we do not know the offered traffic pattern. we also assume that the incoming traffic is not policed or shaped. furthermore, we assu me that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. the manager can then subdivide the applications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offered to the switch. as an added bonus, although we do not assume anyt hing about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additi onal assurances about ou r switch?s performance. table 8 shows examples of qos applications with three tr ansmission priorities, but best effort (p0) traffic may form a fourth class with no bandwidth or la tency assurances. gmac port actually has four total trans mission priorities. zl50410 data sheet 43 zarlink semiconductor inc. a class is capable of offering traffic that exceeds the contracted bandwidth. a well-behaved class offers traffic at a rate no greater than the agreed-upon ra te. by contrast, a misb ehaving class offers tr affic that exceeds the agreed-upon rate. a misbehaving class is formed from an aggregation of misbehaving mi croflows. to achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. however, such leniency must not degrade the quality of service (qos) rece ived by well-behaved classes. as table 8 illustrates, the six traffic types may each have their own distinct propert ies and applications. as shown, classes may receive bandwidth assurances or latency bo unds. in the table, p3, t he highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 mbps of bandwidth at that port. best-effort (p0) traffic forms a fourth class that only re ceives bandwidth when none of the other classes have any traffic to offer. it is also possible to add a fourth class that has strict priority over the ot her three; if this class has even one frame to transmit, th en it goes first. in the zl50410, each rmac port will support two total classes, and the gmac port will support four classes. we will discuss the various modes of schedulin g these classes in the next section. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should rarely lose packets. but poorly behaved users?users who send fram es at too high a rate ? will encounter frame loss, and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and th en all frames in the worst case. table 8 shows that different types of applications may be pl aced in different boxes in the traffic table. for example, casual web browsing fits into the category of high-loss, hi gh-latency-tolerant traffic, whereas voip fits into the category of low-loss, low-latency traffic. 7.2 two qos configurations there are two basic pieces to qos schedu ling in the gmac port of zl50410: st rict priority (sp) or weighted fair queuing (wfq). the only configuration for a rmac and cpu port is strict priority between the queues. goals totalassured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) highest transmission priority, p3 50 mbps apps: phone calls, circuit emulation. latency: < 1 ms. drop: no drop if p3 not oversubscribed. apps: training video. latency: < 1 ms. drop: no drop if p3 not oversubscribed; first p3 to drop otherwise. middle transmission priority, p2 37.5 mbps apps: interactive apps, web business. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed. apps: non-critical interactive apps. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed; firstp2 to drop otherwise. low transmission priority, p1 12.5 mbps apps: emails, file backups. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed. apps: casual web browsing. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed; first to drop otherwise. total 100 mbps table 8 - two-dimensional world traffic zl50410 data sheet 44 zarlink semiconductor inc. 7.2.1 strict priority when strict priority is part of the scheduling algorithm, if a queue has any fram e to transmit, it goes first. for rmac ports, this is an easy way to provide the different service. for all recognizable traffic, the bandwidth is guaranteed to 100% of the line rate. this scheme works as long as the overall high priority bandwidth is not over the line rate and the latency on all the low priority traffi c is don?t care. the strict priority queue in the gmac and cpu ports is similar to rmac ports other than having 4 queues instead of 2 queues . the priority queue p0 can be scheduled only if the priority queue p1 is empty, so as to priority queues p2 and p3. the lowest priority queue is treated as best effort queue. because we do not provide any assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is care fully controlled before entering the zl50410, we do not enforce a fair bandwidth partition by dr opping strict priority traffi c. to summarize, dropping to enforce bandwidth or delay does not apply to strict priori ty or best effort queues. we only drop frames from best effort and strict priority queues when queue size is too long or global / class buffer resources become scarce. 7.2.2 weighted fair queuing in some environments ? for example, in an environment in which delay assurances ar e not required, but precise bandwidth partitioning on small time scales is essential, wfq may be preferable to a strict assurance scheduling discipline. the zl50410 provides this kind of scheduling algorithm on gmac port only. the user sets four wfq ?weights? such that all weights are whole numbers and su m to 64. this provides per-class bandwidth partitioning with granular within 2%. in wfq mode, though we do not assure frame latency, the zl50410 still retains a set of dropping rules that helps to prevent congestion a nd trigger higher level protocol end-to-end flow control. 7.3 wred drop threshold management support to avoid congestion, the weighted random early detecti on (wred) logic drops packets according to specified parameters. the following table summari zes the behavior of the wred logic. px is the total byte count, in the prio rity queue x, can be the strict priori ty queue of rmac ports and higher 3 priority queues for gmac port. the wred logic has two drop leve ls, depending on the value of px. each drop level has defined high-drop and low-drop percent ages, which indicate the minimum and maximum percentages of the data that can be discarded. the x, y z percent can be prog rammed by the register rdrc0, rdrc1. all packets will be dropped only if the system runs out of t he specific buffer resource, per class buffer or per source port buffer. the wred thresholds of each queue can be programmed by the qos control registers (refer to the register group 8). see programming qos registers application note, zlan-42, for more information. 7.4 shaper although traffic shaping is not a primary function of the zl 50410, the chip does implement a shaper for every queue in the gmac port. our goal in shaping is to control th e average rate of traffic ex iting the zl50410. if shaper is enabled, strict priority will be applied to that queue. the priority betwe en two shaped queue is the same as in strict priority scheduling. traffic rate is set using a programmable whole number, no gr eater than 64. for example, if the setting is 32, then the traffic rate transmit out of the shaped queue is 32 /64 * 1000 mbps = 500 mbps. see programming qos register application note, zlan-42, for more information. px > wred_l1 px > wred_l2 bm reject high drop x% 100% 100% low drop y% z% 100% table 9 - wred logic behaviour zl50410 data sheet 45 zarlink semiconductor inc. also, when shaping is enabled, it is possible for a queue to explode in length if fed by a greedy source. the reason is that a shaper is by definit ion not work-conserving; that is, it may hold back from sending a packet even if the line is idle. though we do have global resource management, we do nothing other than per port wred to prevent this situation locally. we assume the traffic is policed at a prior stage to the zl50410 or wred dropping is fine and shall restrain this situation. 7.5 rate control the zl50410 provides a rate control function on its rmac ports. the concept is much the same as shaping, except that it applies to both ingr ess and egress directions and t he control is per port rather than per queue. it provides a way of reducing the total bandwidth of all frames received fr om or transmitted to a port, to a rate below wire speed. as with shaping, the maximum burst size can also be configured. rate control may be a valuable feature on rmac ports in access applications where th e service provider would like to limit the traffic received and tr ansmitted by each port independently of each other, and independently of the physical line rate. the service provider can then provid e differential pricing, based on the negotiated bandwidth requirements for each user. in such applications of the zl50 410, the gmac port is viewed as an uplink port, where rate control is not desired. see rate control application note, zlan-33, for more information. 7.6 buffer management because the number of fdb slots is a scarce resource, and because we w ant to ensure that one misbehaving source port or class cannot harm the performance of a well- behaved source port or clas s, we introduce the concept of buffer management into the zl50410. our buffer manag ement scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in figure 11 on page 46. as shown in the figure, the fdb pool is divided into several parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a te mporary region is necessary, because when the frame first enters the zl50410, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame ca n be received first before su bjecting them to the frame drop discipline after classifying. three priority sections, one for each pair of the first six priority classe s, ensure a programmable number of fdb slots per class. the lowest two classes do not receive any bu ffer reservation. furthermor e, a frame is stored in the region of the fdb corresponding to its class. as we hav e indicated, the eight classe s use only two transmission scheduling queues for rmac ports (four queues for t he gmac & cpu ports), but as far as buffer usage is concerned, there are still ei ght distinguishable classes. another segment of the fdb reserves space for each of the 10 ports ? 9 ports for ethernet and one cpu port (port number 8). each port has it?s own programmable source port reservation. these 10 reserved regions make sure that no well-behaved source port can be bl ocked by another misb ehaving source port. in addition, there is a shared pool, whic h can store any type of frame. the fram e engine allocates the frames first in the three priority sections. when the priori ty section is full or the packet has prio rity 1 or 0, the frame is allocated in the shared pool. once the shared pool is full the frames ar e allocated in the section reserved for the source port. the following registers define the size of each section of the frame data buffer: - pr100_n - port reservation for rmac ports - pr100_cpu - port reservation for cpu port - prg - port reservation for gmac port - sfcb - share fcb size - c1rs - class 1 reserve size (priority 2 & 3) - c2rs - class 2 reserve size (priority 4 & 5) - c3rs - class 3 reserve size (priority 6 & 7) zl50410 data sheet 46 zarlink semiconductor inc. figure 11 - buffer partition scheme see buffer allocation application no te, zlan-47, for more information. 7.6.1 dropping wh en buffers are scarce as already discussed, the wred me chanism may drop frames on output q ueue status. in addition to these reasons for dropping, we also drop frames when global bu ffer space becomes scarce. the function of buffer management is to make sure that su ch dropping causes as little blocking as possible. if a received frame is dispatched to the best effort queue, the buffer managemen t will check on the overall buf fer situation plus the output queue status to decide the frame drop cond ition. if the source port has not e nough buffer for it, the frame will be dropped. if the output queue r each the ucc (unicast congest control) and the shared buffer has run out, the frame will be dropped by b%. if the output queue reach the ucc and the source port reservation is lower than the buffer low threshold, the frame will be dropped. all the dropping f unctions are disabled if the source port is flow control capable. 7.7 flow control basics because frame loss is unacceptable for some applications, the zl50410 provides a flow control option. when flow control is enabled, scarc ity of source port buffer space may trigger a fl ow control signal; this signal tells a source port sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet loss , it also introduces a problem for quality of service. when a source port receives an ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. a single packet destined for a congested out put can block other packet s destined for un-congested outputs. the resulting head-of-line blocking phenomenon mean s that quality of service cannot be assured with high confidence when flow control is enabled. on the other hand, the zl50410 will still prioritize the re ceived frame disregarding the outgoing port flow control capability. if a frame is classified as high priority, it is still subjected to the wred, which means the no-loss on the high priority queue is not guaranteed. to resolve this situation, the user may set the output port wred threshold so high that may never be reached, or program the priority mappin g table in the queue manager to map all the traffic to best effort queue on the flow control capable port. the first method has side impact on the global resource management since the port may hold too much per class resource that is scarce in the system. the second method, by nature, lost the benefit of prioritization. see programming flow control registers applic ation note, zlan-44, for more information. 7.7.1 unicast flow control for unicast frames, flow control is tri ggered by source port resource availa bility. recall that the zl50410?s buffer management scheme allocates a reserved number of fdb sl ots for each source port. if a programmed number of a source port?s reserved fdb slots have been us ed, then flow control xoff is triggered. per class reservation per source port reservation temporary reservation r pri1 r pri2 r pri3 shared pool s r p0 r p1 r p2 r p3 r p4 r p5 r p6 r p7 r p8 (cpu) r p9 zl50410 data sheet 47 zarlink semiconductor inc. xon is triggered when a port is currently being flow controll ed, and all of that port?s reserved fdb slots have been released. note that the zl50410?s per-source-port fdb reservations as sure that a source port t hat sends a single frame to a congested destination will not be flow controlled. 7.7.2 multicast flow control flow control for multicast frames is triggered by a glo bal buffer counter. when the system exceeds a programmable threshold of multicast packets, xoff is triggered. xon is triggered when the system re turns below this threshold. note : if per-port flow control is on, qos performance will be affected. 7.8 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. as the table illustrates, the classes of table 10 are merged in pairs? p3 is used for network management (nm) and expedited forwarding service (ef) frames. classes p2 and p1 correspond to an assured forwarding (af) group of size 2. finally, p0 is for best effort (be) class. features of the zl50410 that correspond to the requirem ents of their associated ietf classes are summarized in the table below. 7.9 failover backplane feature the zl50410 implements a hardware assisted link failure de tection mechanism utilizing a link heart beat (lhb) packet. the lhb packet format is defi ned as a 64-byte mac control frame wi th a user defined opcode. the packet format is illustrated below: where ?xx-xx-xx-xx -xx-xx? is the s ource port mac address and ?yy-yy? is the special opcode defined by register setup (lhbreg0,1). the opcode ?00-01? is reserved for the flow control packet. we recommend opcode ?00-12? for the lhb packet. zl50410 p3 p2 p1 p0 ietf nm+ef af0 af1 be table 10 - mapping to ietf diffserv classes for g mac & cpu ports network management (nm) and expedited forwarding (ef) global buffer reservation for nm and ef shaper for traffic on uplink port no dropping if adm ission controlled assured forwarding (af) global buffer reservation for two af classes shaper for traffic on uplink port random early discard, with programmable levels best effort (be) service only when other queues are idle means that qos not adversely affected shaper for traffic on uplink port random early discard, with programmable levels traffic from flow control enabled ports automatically classified as be table 11 - zl50410 features enabling ietf diffserv standards 01-80-c2-00-00-01 xx-xx-xx- xx-xx-xx 88-08 yy-yy 00-00-... crc zl50410 data sheet 48 zarlink semiconductor inc. the lhb is done between two compatible macs providing this function. a timer parameter will be set for both the receiver and transmitter (lhbtimer). on the transmission side, the mac will monitor the transmissi on activities. if there is no activity for more than the set period, a lhb packet will be sent to its link partner . therefore, there should always be at least one packet transmitted from the mac fo r every period specified. on the receiving side, the mac will al so monitor the activity. if there is no good packet received for more than 2x the set period, an alarm will be raised to the cpu. the lhb packet is only used by the zl50410 to reset the timeout counter, it is ignored otherwise (i.e . not passed on within the system). see the failover protection application note, zlan-43, for more information. 8.0 port trunking see port trunking application note , zlan-48, for more information. 8.1 features and restrictions a port group (i.e. trunk) can include up to 8 physical ports, all of the ports in a group can be in the same zl50410 or in multiple zl50410 to form a fault tolerant link. there are eight trunk groups total. load distribution among the ports in a trunk for unicast is performed using hashing based on source mac address and destination mac address. three other options include source mac address only, destination mac address only, and source port (in bidirectional ring mode only). l oad distribution for multicast is performed similarly. if a vlan includes any of the ports in a trunk group, all the ports in that trunk group should be in the same vlan member map. the zl50410 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the zl50410 can redistribute the traffic ov er to the remaining ports in the trunk with software assistance. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status fiel d says that the destination port found belongs to a trunk, then the trunk group number is retrieved. the source port of the packet is chec ked against the destination trunk group. if the source port belongs to the destination trunk group, the packet is discarded. a hash key, based on some combination of the source and destination mac addresses for the current packet, selects the appropriate forwarding port, as specified in the trunk_hash registers. each trunk has eight trunk_hash registers which selects one of the potential eight outgoing ports. the hash key provides a pseudo flow identifier which force the same flow to the same destination flow . as a result, the packet will always arrive in order. 8.3 multicast packet forwarding for multicast packet forwarding, the device must determi ne the proper set of ports from which to transmit the packet based on the vlan and hash key. three functions are required in order to distribute multic ast packets to the appropriate destination ports in a port trunking environment. ? determining the vlan group it is forwarding port per group. ? the source port/group must be excluded from the forwarding. ? select one port per trunk group to forward the packet to. this selection is based on hash key described in previous section. zl50410 data sheet 49 zarlink semiconductor inc. for example, port 0,1 and 2 belong to trunk group 0 and port 3 and 4 belong to trunk group 1. a single vlan is established in this system with port 0,1,2,3,4,5 and 6 as the members in the vlan. when a multicast packet is sent in from port 3, the zl50410 select port 0,1,2,3,4,5 and 6 as potential dest ination based on the vlan. then port 3 and 4 are removed because they belong to the source port group (trunk group 1) . two ports from trunk group 0 will be removed based on the hash key. in this example, we assume port 0 and 1 are removed. as a result, port 2,5 and 6 are the only outgoing ports for this multicast packet. 9.0 traffic mirroring see traffic mirroring application no te, zlan-50, for more information. 9.1 mirroring features packets can be mirrored (duplicated) for network monitor purpose and/or network debug purpose. three types of mirroring is available in zl50410. 1. source or destination mac address based 2. flow based 3. port based in source or destination mac address bas ed mirroring, the ?m? bit of the mirr oring mac address in the mct is set. also, the user need to specify the mirroring mac address is source or desti nation of the packet. if source is selected, any packet received with the mirroring ma c address as source mac address will be copied to the mirrored port. in the same way, if destination is se lected, any packet received with mirroring mac address as destination mac address will be copied to the mirrored port. in flow based mirroring, a flow is established based on the source and destination mac address pair. when enabled, a packet with source and destination address match the pre-pr ogrammed source and destination mac address pair will be copied to the mirrored port. in re verse direction (source and destination match pre programmed destination and source), the flow can also be enabled and the frame will be copied to the mirrored port. in port based mirroring, traffic from any rmac port can be mirrored to any rmac port. the traffic from the source port can be either ingress or egress traffic. up to two por ts can be setup as mirrored port s. as a result, the traffic (both ingress and egress) of a specific port can be monitor ed by setting up both mirrored ports. once a port is setup as mirrored port, it cannot be used for regular traffic. the mirrored port can be any port in the zl50410. 9.2 using port mirroring for loop back to perform remote loop back test, port mirroring can be used to bounce back t he packet to the source port to check the data path. the cpu needs to setup the remote device through the co mmand channel to enable port mirroring in the remote device. a cpu packet is send to the port in test in device a. the packet will be forwarded to the test port, external cable, the destination port in device b, and loop back to itself, back to the cable and go back to device a and the cpu. this way, the whole channel can be tested. zl50410 data sheet 50 zarlink semiconductor inc. figure 12 - remote loopback test 10.0 clocks 10.1 cloc k requirements 10.1.1 system clock (sclk) speed requirement sclk is the primary clock for the zl50410 device. the speed requirement is based on the system configuration. below is a table for a few configuration. 10.1.2 rmac reference clock (m_clk) speed requirement m_clk is a 50 mhz clock used for the rmac ports (ports 0-7) and cpu port (port 8). if none of the rmac ports are confi gured in rmii mode or reverse mii mo de, a different clock frequency can be applied to m_clk, as long as it's less than 50 mhz. in this case, register usd must be set to provide an internal 1usec timing. 10.1.3 gmac reference cloc k (gref_clk) speed requirement gref_clk is a 125 mhz reference clock required for the gmac port (port 9). if the device is in a 9 port 10/100 configuration on ly, gref_clk can be a lower frequency clock and can be connected to m_clk to reduce the number of clock sources. if port 9 is not being used, gref_clk can be left unconnected. 10.1.4 jtag test clock (tck) speed requirements tck is a clock used for the jtag port. the frequency on this clock can vary. refer to ?jtag (ieee 1149.1-2001)? on page 135 for the frequency range. configuration minimum sclk speed required 8 port 10/100m + 1 port 1000m 100 mhz 6-9 ports 10/100m 50 mhz 1-5 ports 10/100m 25 mhz table 12 - sclk speed requirements device b device a cpu zl50410 data sheet 51 zarlink semiconductor inc. 10.2 cl ock generation 10.2.1 mdc mdc is used for the mii management interface and cl ocks data on mdio. it is generated by the device from m_clk and is equal to 500 khz (m_clk/100). if a different speed clock other than 50mhz is used on m_clk, the usd register must be programmed to reset mdc. 10.2.2 scl scl is used for the i2c interface and clocks data on sda. it is generated by the device from m_clk and is equal to 50khz (m_clk/1000). if a different speed clock other than 50mhz is used on m_clk, the usd register must be programmed to reset scl. 10.2.3 ethernet interface clocks if the rmac ports are configured in reverse mii mo de, txclk and rxclk are generated from m_clk and are equal to m_clk/2 for 100m mode or m_clk/20 for 10m mode. m_clk needs to be a 50 mhz clock in this mode. if the rmac ports are configured in reverse gpsi mode, txclk and rxclk are generated from m_clk and are equal to m_clk/2 for 10m mode. m_clk needs to be a 20 mhz clock in this mode and usd must be programmed accordingly. for the cpu port in serial+mii mode, txclk and rxclk are generated from m_clk and are equal to m_clk/2 for 100m mode or m_clk/20 for 10m mode. m_clk needs to be a 50mhz clock in this mode. the gigabit port generates an external txclk interface cloc k in gmii mode. it is equal to the 125 mhz gref_clk. if the gmac port is configured in reverse mii mode, rxclk is generated from gref_clk and is equal to gref_clk/2 for 100m mode (no support for 10m reverse mii mode). gref_clk needs to be a 50 mhz clock in this mode. zl50410 data sheet 52 zarlink semiconductor inc. 11.0 hardware statistics counters 11.1 hardware stat istics counters list zl50410 hardware provides a full set of statistics counte rs for each ethernet port. the cpu accesses these counters through the cpu interface. all hardware counte rs are rollover counters. w hen a counter rolls over, the cpu is interrupted, so that long-term statistics may be k ept. the mac detects all statistics, except for the delay exceed discard counter (detected by buffer manager) a nd the filtering counter (det ected by queue manager). the following is the wrapped signal sent to the cpu through the command block. 63 30 29 0 other status bits status wrapped signal b[0] 0-d bytes sent (d) b[1] 1-l unicast frame sent b[2] 1-u frame send fail b[3] 2-i flow control frames sent b[4] 2-u non-unicast frames sent b[5] 3-d bytes received (good and bad) (d) b[6] 4-d frames received (good and bad) (d) b[7] 5-d total bytes received (d) b[8] 6-l total frames received b9] 6-u flow control frames received b[10] 7-l multicast frames received b[11] 7-u broadcast frames received b[12] 8-l frames with length of 64 bytes b[13] 8-u jabber frames b[14] 9-l frames with length between 65-127 bytes b[15] 9-u oversize frames b[16] a-l frames with length between 128-255 bytes b[17] a-u frames with length between 256-511 bytes b[18] b-l frames with length between 512-1023 bytes b[19] b-u frames with length between 1024-1528 bytes zl50410 data sheet 53 zarlink semiconductor inc. b[20] c-l fragments b[21] c-u1 alignment error b[22] c-u undersize frames b[23] d-l crc b[24] d-u short event b[25] e-l collision b[26] e-u drop b[27] f-l filtering counter b[28] f-u1 delay exceed discard counter b[29] f-u late collision notation: x-y x: address in the contain memory y: size and bits for the counter d: d word counter l: 24 bits counter bit [23:0] u: 8 bits counter bit [31:24] u1: 8 bits counter bit [23:16] l: 16 bits counter bit [15:0] u: 16 bits counter bit [31:16] zl50410 data sheet 54 zarlink semiconductor inc. 11.2 ieee 802.3 hub management (rfc 1516) 11.2.1 event counters 11.2.1.1 readableoctet counts number of bytes (i.e. octets) contained in good valid frames received. 11.2.1.2 readableframe counts number of good valid frames received. 11.2.1.3 fcserrors counts number of valid frames received with bad fcs. 11.2.1.4 alignmenterrors counts number of valid frames received wi th bad alignment (not byte-aligned). frame size: > 64 bytes, < 1522 bytes if vlan tagged; (< 1518 bytes if not vlan tagged) (< buf_limit if enabled for this port) no fcs (i.e. checksum) error no collisions frame size: > 64 bytes, < 1522 bytes if vlan tagged; (< 1518 bytes if not vlan tagged) (< buf_limit if enabled for this port) no fcs error no collisions frame size: > 64 bytes, < 1522 bytes if vlan tagged; (< 1518 bytes if not vlan tagged) (< buf_limit if enabled for this port) no framing error no collisions frame size: > 64 bytes, < 1522 bytes if vlan tagged; (< 1518 bytes if not vlan tagged) (< buf_limit if enabled for this port) no framing error no collisions zl50410 data sheet 55 zarlink semiconductor inc. 11.2.1.5 frametoolongs counts number of frames receiv ed with size exceeding the maximum allowable frame size. 11.2.1.6 shortevents counts number of frames received with size less than the length of a short event. 11.2.1.7 runts counts number of frames rece ived with size under 64 bytes, but grea ter than the length of a short event. 11.2.1.8 collisions counts number of collision events. 11.2.1.9 lateevents counts number of collision events that occurred late (after lateeventthreshold = 64 bytes). frame size: > 64 bytes, > 1522 bytes if vlan tagged; ( > 1518 bytes if not vlan tagged) ( > buf_limit if enabled for this port) fcs error: don?t care framing error: don?t care no collisions frame size: < 10 bytes fcs error: don?t care framing error: don?t care no collisions frame size: > 10 bytes, < 64 bytes fcs error: don?t care framing error: don?t care no collisions frame size: any size frame size: any size events are also counted by collision counter zl50410 data sheet 56 zarlink semiconductor inc. 11.2.1.10 verylongevents counts number of frames received with size larger than jabber lockup protection timer (tw3). 11.2.1.11 da taratemisatches for repeaters or hub application only. 11.2.1.12 autopartitions for repeaters or hub application only. 11.2.1.13 totalerrors sum of the following errors: ? fcserrors ? alignmenterrors ? frametoolong ? shortevents ? lateevents ? verylongevents ? dataratemisatches 11.3 ieee 802.1 brid ge management (rfc 1286) 11.3.1 event counters 11.3.1.1 inframes counts number of frames receiv ed by this port or segment. note: a frame received by this port is only counted by this co unter if and only if it is for a protocol being processed by the local bridge function. 11.3.1.2 outframes counts number of frames tr ansmitted by this port. note : a frame transmitted by this port is onl y counted by this counter if and on ly if it is for a protocol being processed by the loca l bridge function. 11.3.1.3 indiscards counts number of valid frames received which were di scarded (i.e., filtered) by the forwarding process. 11.3.1.4 de layexceededdiscards counts number of frames discarded due to ex cessive transmit delay through the bridge. 11.3.1.5 mt uexceededdiscards counts number of frames disc arded due to excessive size. frame size: > jabber zl50410 data sheet 57 zarlink semiconductor inc. 11.4 rmon ? ethernet statistic group (rfc 1757) 11.4.1 event counters 11.4.1.1 drop events counts number of times a packet is dropped, because of lack of available resources. does not include all packet dropping -- for example, random early drop for quality of service support. 11.4.1.2 octets counts the total number of octets (i .e. bytes) in any frames received. 11.4.1.3 broadcastpkts counts the number of good frames receiv ed and forwarded with broadcast address. does not include non-broadcast multicast frames. 11.4.1.4 multicastpkts counts the number of good frames receiv ed and forwarded with multicast address. does not include broadcast frames. 11.4.1.5 crcalignerrors counts number of frames received with fcs or alignment errors 11.4.1.6 undersizepkts counts number of frames received with size less than 64 bytes. frame size: > 64 bytes, < 1522 bytes if vlan tagged; (< 1518 bytes if not vlan tagged) (< buf_limit if enabled for this port) no collisions: frame size: < 64 bytes, no fcs error no framing error no collisions zl50410 data sheet 58 zarlink semiconductor inc. 11.4.1.7 oversizepkts counts number of frames receiv ed with size exceeding the maximum allowable frame size. 11.4.1.8 fragments counts number of frames received with si ze less than 64 bytes and with bad fcs. 11.4.1.9 jabbers counts number of frames receiv ed with size exceeding maximum frame size and with bad fcs. frame size: > 1522 bytes if vlan tagged; ( > 1518 bytes if not vlan tagged) ( > buf_limit if enabled for this port) fcs error don?t care framing error don?t care no collisions frame size: < 64 bytes framing error don?t care no collisions frame size: > 1522 bytes if vlan tagged; ( > 1518 bytes if not vlan tagged) ( > buf_limit if enabled for this port) framing error don?t care no collisions zl50410 data sheet 59 zarlink semiconductor inc. 11.4.1.10 collisions counts number of collision events detected. only a best estimate since collisions can only be detect ed while in transmit mode, but not while in receive mode. 11.4.1.11 packet count for different size groups six different size groups ? one counter for each: pkts64octets for any packet with size = 64 bytes pkts65to127octets for any packet with size from 65 bytes to 127 bytes pkts128to255octets or any packet with size from 128 bytes to 255 bytes pkts256to511octets for any packet with size from 256 bytes to 511 bytes pkts512to1023octets for any packet with size from 512 bytes to 1023 bytes pkts1024to1518octets for any packet with size from 1024 bytes to 1518 bytes (to 1522 with vlan tag; to buf_limit if enabled for this port) counts both good and bad packets. 11.5 miscel laneous counters in addition to the statistics groups de fined in previous sections, the zl50410 has other statistics counters for its own purposes. we have two counters for flow control ? one c ounting the number of flow c ontrol frames received, and another counting the number of flow control frames sent . we also have two counters , one for unicast frames sent, and one for non-unicast frames sent. a broadcast or multicast frame quali fies as non-unicast. furthermore, we have a counter called ?frame send fail.? this keeps track of fifo under-runs, late collis ions, and collisions that have occurred 16 times. frame size: any size zl50410 data sheet 60 zarlink semiconductor inc. 12.0 register definition 12.1 zl50410 register description register description cpu addr (hex) r/w i2c addr (hex) default notes 0. ethernet port control registers (sub stitute [n] with port number (0..9)) ecr1pn port control register 1 for port n 000+2n r/w 000+n 0c0 ecr2pn port control register 2 for port n 001+2n r/w 00a+n 000 ecr3pn port control register 3 for port n 080+2n r/w 014+n 000 ecr4pn port control register 4 for port n 081+2n r/w 01e+n 018 buf_limit frame buffer limit 036 r/w na 040 fcc flow control grant period 037 r/w na 003 1. vlan control registers (substitut e [n] with port number (0..9)) avtcl vlan type code register low 100 r/w 028 000 avtch vlan type code register high 101 r/w 029 081 pvmapn_0 port n configuration register 0 102+4n r/w 02a+n 0ff pvmapn_1 port n configuration register 1 103+4n r/w 034+n 0ff pvmapn_3 port n configuration register 3 105+4n r/w 03e+n 000 pvmode vlan operating mode 170 r/w 048 000 2. trunk control registers (substitute [n] with trunk group number ( 0..7 )) trunkn trunk group n 200+n r/w na 000 trunkn_hash10 trunk group n hash 10 destination port 208+4n r/w na 000 trunkn_hash32 trunk group n hash 32 destination port 209+4n r/w na 000 trunkn_hash54 trunk group n hash 54 destination port 20a+4n r/w na 000 trunkn_hash76 trunk group n hash 76 destination port 20b+4n r/w na 000 table 13 - register description zl50410 data sheet 61 zarlink semiconductor inc. pvlan_pn private vlan edge (protected ports) port n egress portmap 220+n r/w na 000 multicast_hashn-0 multicast hash result n mask byte 0 228+2n r/w na 0ff multicast_hashn-1 multicast hash result n mask byte 1 229+2n r/w na 0ff 3. cpu port configuration mac0 cpu mac address byte 0 300 r/w na 000 mac1 cpu mac address byte 1 301 r/w na 000 mac2 cpu mac address byte 2 302 r/w na 000 mac3 cpu mac address byte 3 303 r/w na 000 mac4 cpu mac address byte 4 304 r/w na 000 mac5 cpu mac address byte 5 305 r/w na 000 int_mask0 interrupt mask 0 306 r/w na 000 intp_maskn interrupt mask for mac port 2n, 2n+1 310+n r/w na 000 (n=0..4) rqs receive queue select 323 r/w na 000 rqss receive queue status 324 ro na na mac01 increment mac port 0,1 address 325 r/w na 000 mac23 increment mac port 2,3 address 326 r/w na 000 mac45 increment mac port 4,5 address 327 r/w na 000 mac67 increment mac port 6,7 address 328 r/w na 000 mac9 port 9 mac address byte 5 329 r/w na 000 cpuqins[6:0] 330-336 r/w na 000 cpuqinsrpt 337 ro na na cpugrnhdl[1:0] 338-339 ro na na cpurlsinfo[4:0] 33a-33e r/w na 000 cpugrnctr 33f r/w na 000 4. search engine configurations agetime_low mac address aging time low 400 r/w 049 05c register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 62 zarlink semiconductor inc. agetime_high mac address aging time high 401 r/w 04a 000 se_opmode search engine operating mode 403 r/w na 000 5. global qos control qosc qos control 500 r/w 04b 000 ucc unicast congestion control 510 r/w 068 006 mcc multicast congestion control 511 r/w 069 006 mccth multicast congestion threshold 512 r/w na 003 rdrc0 wred drop rate control 0 513 r/w 090 000 rdrc1 wred drop rate control 1 514 r/w 091 000 rdrc2 wred drop rate control 2 515 r/w na 000 sfcb share fcb size 518 r/w 074 000 c1rs class 1 reserve size 519 r/w 075 000 c2rs class 2 reserve size 51a r/w 076 000 c3rs class 3 reserve size 51b r/w 077 000 avpml vlan priority map low 530 r/w 056 000 avpmm vlan priority map middle 531 r/w 057 000 avpmh vlan priority map high 532 r/w 058 000 avdm vlan discard map 533 r/w 05c 000 tospml tos priority map low 540 r/w 059 000 tospmm tos priority map middle 541 r/w 05a 000 tospmh tos priority map high 542 r/w 05b 000 tosdml tos discard map 543 r/w 05d 000 user_protocol_n user define protocol n 550+n r/w 0b3+n 000 (n=0..7) user_protocol_ force_discard user define protocol 0 to 7 force discard enable 558 r/w 0bb 000 wlpp10 well known logic port 0 and 1 priority 560 r/w 0a8 000 register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 63 zarlink semiconductor inc. wlpp32 well known logic port 2 and 3 priority 561 r/w 0a9 000 wlpp54 well known logic port 4 and 5 priority 562 r/w 0aa 000 wlpp76 well known logic port 6 and 7 priority 563 r/w 0ab 000 wlpe well known logic port 0 to 7 enable 564 r/w 0ac 000 wlpfd well known logic port 0 to 7 force discard enable 565 r/w 0ad 000 user_portn_low user define logical port n low 570+2n r/w 092+n 000 (n=0..7) user_portn_high user define logical port n high 571+2n r/w 09a+n 000 user_port1:0_ priority user define logic port 0 and 1 priority 590 r/w 0a2 000 user_port3:2_ priority user define logic port 2 and 3 priority 591 r/w 0a3 000 user_port5:4_ priority user define logic port 4 and 5 priority 592 r/w 0a4 000 user_port7:6_ pri ority user define logic port 6 and 7 priority 593 r/w 0a5 000 user_port_ enable[7:0] user define logic port 0 to 7 e n a b l e 594 r/w 0a6 000 user_port_ force_discard[7:0] user define logic port 0 to 7 force discard enable 595 r/w 0a7 000 rlowl user define range low bit [7:0] 5a0 r/w 0ae 000 rlowh user define range low bit [15:8] 5a1 r/w 0af 000 rhighl user define range high bit [7:0] 5a2 r/w 0b0 000 rhighh user define range high bit [15:8] 5a3 r/w 0b1 000 rpriority user define range priority 5a4 r/w 0b2 000 6. misc configuration register mii_op0 mii register option 0 600 r/w 0bc 000 mii_op1 mii register option 1 601 r/w 0bd 000 register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 64 zarlink semiconductor inc. fen feature registers 602 r/w 0be 010 miic0 mii command register 0 603 r/w na 000 miic1 mii command register 1 604 r/w na 000 miic2 mii command register 2 605 r/w na 000 miic3 mii command register 3 606 r/w na 000 miid0 mii data register 0 607 ro na na miid1 mii data register 1 608 ro na na usd one micro second divider 609 r/w na 000 device device id and test 60a r/w na 002 sum eeprom checksum register 60b r/w 0ff 000 lhbtimer link heart beat time out timer 610 r/w na 000 lhbreg0 lhb control field value[7:0] 611 r/w na 000 lhbreg1 lhb control field value [15:8] 612 r/w na 000 fmaccreg0 forced mac control field value [7:0] 613 r/w na 000 fmaccreg1 forced mac control field value [15:8] 614 r/w na 000 fcb_base_addr0 fcb base address register 0 620 r/w 0bf 000 fcb_base_addr1 fcb base address register 1 621 r/w 0c0 060 fcb_base_addr2 fcb base address register 2 622 r/w 0c1 000 7. port mirroring controls mirror_dest_mac0 mirror destination mac address 0 700 r/w na 000 mirror_dest_mac1 mirror destination mac address 1 701 r/w na 000 mirror_dest_mac2 mirror destination mac address 2 702 r/w na 000 mirror_dest_mac3 mirror destination mac address 3 703 r/w na 000 mirror_dest_mac4 mirror destination mac address 4 704 r/w na 000 register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 65 zarlink semiconductor inc. mirror_dest_mac5 mirror destination mac address 5 705 r/w na 000 mirror_src_mac0 mirror source mac address 0 706 r/w na 000 mirror_src_mac1 mirror source mac address 1 707 r/w na 000 mirror_src_mac2 mirror source mac address 2 708 r/w na 000 mirror_src_mac3 mirror source mac address 3 709 r/w na 000 mirror_src_mac4 mirror source mac address 4 70a r/w na 000 mirror_src_mac5 mirror source mac address 5 70b r/w na 000 mirror_control port mirror control register 70c r/w na 000 rmac_mirror0 rmac mirror 0 710 r/w na 000 rmac_mirror1 rmac mirror 1 711 r/w na 000 8. per port qos control fcrn flooding control register n 800+n r/w 04c+n 000 (n=0..9) bmrcn broadcast/multicast rate control n 820+n r/w 05e+n 000 pr100_n port reservation for rmac ports (n=0..7) 840+n r/w 06a+n 006 ?d1536/1 6=?d96, ?d96>>4= ?h6 pr100_cpu port reservation for cpu port 848 r/w 073 006 ?d96 prg port reservation for gmac port 849 r/w 072 024 ?d96x6=? d576, ?d576>>4 =?h24 pth100_n port threshold for rmac ports (n=0..7) 860+n r/w 0c2+n 003 ? pth100_cpu port threshold for cpu port 868 r/w 0cb 003 ? pthg port threshold for gmac port 869 r/w 0ca 012 ? register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 66 zarlink semiconductor inc. qoscn qos control n 880+n r/w 078-08f 000 (n=0..39) na e. system diagnostic dtsrl test register low e00 r/w na 000 dtsrm test register medium e01 r/w na 001 testout0 testmux output [7:0] e02 r/o na na testout1 testmux output [15:8] e03 r/o na na mask0 mask timeout 0 e10 r/w 0f6 000 mask1 mask timeout 1 e11 r/w 0f7 000 mask2 mask timeout 2 e12 r/w 0f8 000 mask3 mask timeout 3 e13 r/w 0f9 000 mask4 mask timeout 4 e14 r/w 0fa 000 bootstrap[2:0] bootstrap read back e80-e82 ro na na prtfsmstn ethernet port n status read back e90+n ro na na (n=0..9) prtqosstn rmac port n qos and queue status ea0+n ro na na (n=0..7) prtqosst8a cpu port qos and queue status a ea8 ro na na prtqosst8b cpu port qos and queue status b ea9 ro na na prtqosst9a gmac port qos and queue status a eaa ro na na prtqusst9b gmac port qos and queue status b eab ro na na classqosst class buffer status eac ro na na prtintctr buffer interrupt status ead r/w na 000 qmctrln ports queue control status eb0+n r/w na 000 (n=0..9) qctrl ports queue control eba r/w na 000 bmbistr0 memory bist result ebb r/o na na bmbistr1 memory bist result ebc r/o na na bmcontrol memory control ebd r/w na 00f buff_rst buffer reset pool ec0 r/w na 000 fcbheadptr0 fcb head pointer [7:0] ec1 r/w na 000 register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 67 zarlink semiconductor inc. 12.2 directly accessed registers 12.2.1 index_reg0 ? address for indirectly accessed register addresses (8/16 bits) ? address = 0 (write only) ? in 16-bit or serial m ode: address bits [15:0] ? in 8-bit mode: address bits [7:0] 12.2.2 index_reg1 (only needed for 8-bit mode) ? address for indirectly accessed register addresses (8 bits) ? address = 1 (write only) ? in 16-bit or serial mode: na ? in 8-bit mode: address bits [15:8] fcb_head_ptr1 fcb head pointer [15:8] ec2 r/w na 000 fcb_tail_ptr0 fcb tail pointer [7:0] ec3 r/w na 000 fcb_tail_ptr1 fcb tail pointer [15:8] ec4 r/w na 000 fcb_num0 fcb number [7:0] ec5 r/w na 000 fcb_num1 fcb init start and fcb number [14:8] ec6 r/w na 006 bm_rlsff_ctrl read control register ec7 r/w na 000 bm_rlsff_info0 bm_rlsfifo_info[7:0] ec8 ro na na bm_rlsff_info1 bm_rlsfifo_info[15:8] ec9 ro na na bm_rlsff_info2 bm_rlsfifo_info[23:16] eca ro na na bm_rlsff_info3 bm_rlsfifo_info[31:24] ecb ro na na bm_rlsff_info4 bm_rlsfifo_info[39:32] ecc ro na na bm_rlsff_info5 fifo_cnt[2:0],bm_rlsfifo_inf o[44:40] ecd ro na na f. system control gcr global control register f00 r/w na 000 dcr device control register f01 ro na na dcr1 device control register 1 f02 ro na na dpst device port status register f03 r/w na 000 dtst data read back register f04 ro na na da da register fff ro na 0da register description cpu addr (hex) r/w i2c addr (hex) default notes table 13 - register description (continued) zl50410 data sheet 68 zarlink semiconductor inc. 12.2.3 data_frame_reg ? data of indirectly accessed registers (8 bits) ? address = 2 (read/write) 12.2.4 control_frame_reg ? cpu transmit/receive switch frames (8/16 bits) ? address = 3 (read/write) ?format: 8-byte of frame status (frame size, source port #, vlan tag) frame data (size should be in multiple of 8-byte) 12.2.5 command&status register ? cpu interface commands and status (8 bits) ? address = 4 (read/write) ? when the cpu writes to this register ? when the cpu reads this register: bit [0]: set control frame receive buffer ready, after cpu writes a complete frame into the buffer. this bit is self-cleared. bit [1]: set control frame transmit buffer1 ready, afte r cpu reads out a complete frame from the buffer. this bit is self-cleared. bit [2]: set control frame transmit buffer2 ready, afte r cpu reads out a complete frame from the buffer. this bit is self-cleared. bit [3]: set this bit to indicate cpu received a whole frame (transmit fifo frame receive done), and flushed the rest of frame fragment, if occurs. this bit will be self-cleared. bit [4]: set this bit to indicate that the following writ e to the receive fifo is th e last one (eof). this bit will be self-cleared. bit [5]: set this bit to re-start the data that is sent from the cpu to receive fi fo (re-align). this feature can be used for software debug. for normal operation must be '0'. bits [7:6]: reserved. must be '0' bit [0]: control frame receive buffer ready, cpu can write a new frame 1 ? cpu can write a new control command 1 0 ? cpu has to wait until this bit is 1 to write a new control command 1 bit [1]: control frame transmit buffer1 ready for cpu to read 1 ? cpu can read a new control command 1 0 ? cpu has to wait until this bit is 1 to read a new control command bit [2]: control frame transmit buffer2 ready for cpu to read 1 ? cpu can read a new control command 1 0 ? cpu has to wait until this bit is 1 to read a new control command bit [3]: transmit fifo has data for cpu to read (txfifo_rdy) bit [4]: receive fifo has space for incoming cpu frame (rxfifo_spok) bit [5]: transmit fifo end of frame (txfifo_eof) bits [7:6]: reserved zl50410 data sheet 69 zarlink semiconductor inc. 12.2.6 interrupt register ? interrupt sources (8 bits) ? address = 5 (read/write) 12.2.7 control command frame buffer1 access register ? cpu transmit/receive control frames (8/16 bits) ? address = 6 (read/write) ? when cpu writes to this register: data is written to the control command frame receive buffer ? when cpu reads this register: data is read from the control command frame transmit buffer1 12.2.8 control command frame buffer2 access register ? cpu receive control frames (8/16 bits) ? address = 7 (read only) ? when cpu reads this register: data is read from the control command frame transmit buffer2 12.3 indirectly accessed registers 12.3.1 (group 0 address) mac ports group 12.3.1.1 ecr1pn: port n control register i2c address 000+n; cpu address:0000+2n (n = port number) accessed by cpu and i2c (r/w) port 0 ? 7 & 9: (rmac & gmac ports) bit [0]: cpu frame interrupt bit [1]: control frame 1 interrupt. control fr ame receive buffer1 has data for cpu to read bit [2]: control frame 2 interrupt. control fr ame receive buffer2 has data for cpu to read bits [6:3]: reserved bit [7]: device timeout detected interrupt note: this bit is not self-clear ed. after reading, the cpu has to clear the bit writing 0 to it. bit [0] flow control 0 - enable (default) 1 - disable bit [1] duplex mode 0 - full duplex (default) 1 - half duplex - only in 10/100 mode bit [2] speed 0 - 100 mbps (default) 1 - 10 mbps zl50410 data sheet 70 zarlink semiconductor inc. port 8: (cpu port) bits [4:3] 00 - enable auto-negotiation (default) this enables hardware state machine for auto-negotiation. 01 - limited disable auto-negotiation this disables hardware state machine for speed auto-negotiation (use ecr1pn[2:0] for configuration). hardware will still poll phy for link status. 10 - force link down disable the port. hardware does not talk to phy. 11 - force link up the configuration in ecr1pn[2:0] is used for (speed/duplex/flow control) setup. hardware does not talk to phy. bit [5] asymmetric flow control enable. 0 ? disable asymmetric flow control (default) 1 ? enable asymmetric flow control when this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it?s receiver inte rprets and processes flow control frames. bits [7:6] ss - spanning tree state (ieee 802.1d spanning tree protocol) 00 - blocking: frame is dropped 01 - listening: frame is dropped 10 - learning: frame is dropped. source mac address is learned. 11 - forwarding: frame is forwarded. s ource mac address is learned. (default) 8/16-bit or serial only modes bit [5:0] reserved bits [7:6] ss - spanning tree state (ieee 802.1d spanning tree protocol) 00 - blocking: frame is dropped 01 - listening: frame is dropped 10 - learning: frame is dropped. source mac address is learned. 11 - forwarding: frame is forwarded. s ource mac address is learned. (default) serial + mii mode bit [0] flow control 0 - enable (default) 1 - disable bit [1] duplex mode must be 0 - full duplex (default) bit [2] speed 0 - 100 mbps (default) 1 - 10 mbps bit [3] 1 - mii port up the configuration in ecr1pn[2:0] is used for (speed/duplex/flow control) setup. 0 - mii port down note: bit [4] must be ?1?. bit [4] must be ?1?. zl50410 data sheet 71 zarlink semiconductor inc. 12.3.1.2 ecr2pn: port n control register i2c address: 00a+n; cpu address:0001+2n (n = port number) accessed by cpu and i2c (r/w) bit [5] asymmetric flow control enable. 0 ? disable asymmetric flow control (default) 1 ? enable asymmetric flow control when this bit is set and flow control is on (bit [0] = 0), the device does not send out flow control frames, but it?s receiver inte rprets and processes flow control frames. bits [7:6] ss - spanning tree state (ieee 802.1d spanning tree protocol) 00 - blocking: frame is dropped 01 - listening: frame is dropped 10 - learning: frame is dropped. source mac address is learned. 11 - forwarding: frame is forwarded. s ource mac address is learned. (default) bit [0]: filter untagged frame 0: disable (default) 1: all untagged frames from this port ar e discarded or follow security option when security is enable bit [1]: filter tag frame 0: disable (default) 1: all tagged frames from this port are discarded or follow security option when security is enable bit [2]: learning disable 0: learning is enabled on this port (default) 1: learning is disabled on this port bit [3]: rate control timer select (rmac ports only) 0: 10 microsecond refreshing time (default) 1: 1 millisecond refreshing time bit [4] force vlan tag out 0: disable (default) 1: enable if this feature is enabled, a packet le aving the device will always have a vlan tag. only applicable in tagged-based vl an mode (pvmode[0]=?1?). in port-based vlan mode (pvmode[0]=?0?), this bit must be 0. bit [5] do not change vlan tag. this overrides pvmapnn_3 bit [2]. if this bit is set, no tag will be replaced nor removed. 0: disable (default) 1: enable zl50410 data sheet 72 zarlink semiconductor inc. 12.3.1.3 ecr3pn: port n control register i2c address: 014+n; cpu address:0080+2n (n = port number) accessed by cpu and i2c (r/w) bits [7:6] security enable. the zl50410 checks t he incoming data for one of the following conditions: ? if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingres s port is not the same as the port associated with the mac address in the mac table. ? a mac address is defined as secure when its entry at mac table has static status and bit 0 is set to 1. mac address bit 0 (the first bit transmitted) indicates whether the a ddress is unicast or multicast. as source addresses are always unicas t bit 0 is not used (always 0). zl50410 uses this bit to define secure mac addresses. ? if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table or the mac address is not associated to the ingress port. if any one of the conditions is met, the packet is forwarded based on these setting. 00 ? disable port security, forward packets as usual. (default) 01 ? discard violating packets 10 ? forward violating packets as usua l and also to the cpu for inspection 11 ? forward violating packets to the cpu for inspection it also checks for one of the following additional conditions: ? if the port is configured to filter untagged frames and an untagged frame arrives, or ? if the port is configured to filter ta gged frames and a tagged frame arrives, or ? if the packet has the source mac address on the source mac address filter list, or ? if the packet has the destination ma c address on the destination mac address filter list if any one of the conditions is met, the packet will be handled according to: 0x ? discard violating packets 1x ? forward violating packets to cpu for inspection bit [0]: enable receiving short frame < 64b 0: disable (default) 1: allow receiving short frame with correct crc. bit [1]: enable receiving long frame > 1522 0: disable (default) 1: allow receiving long frame that are <= buf_limit value bit [2]: enable pad frame to 64b when transmitted 0: allow padding to 64b (default) 1: disable bit [3]: enable compress preamble 0: send standard preamble (default) 1: only one byte preamble+sfd bits [6:4] number of bytes removed from the inter-frame gap (ifg). (default 0x0) zl50410 data sheet 73 zarlink semiconductor inc. 12.3.1.4 ecr4pn: port n control register i2c address: 01e+n; cpu address:0081+2n (n = port number) accessed by cpu and i2c (r/w) port 0 ? 7: (rmac ports) bit [7] link heart beat transmit (rmac ports only) 0: disable (default) 1: enable bit [0]: enable txclk output. active high 0: disable (default) 1: mn_txclk pin becomes output in gpsi or mii mode bit [1]: enable rxclk output. active high 0: disable (default) 1: mn_rxclk pin becomes output in gpsi or mii mode bit [2]: internal loopback. 0: disable (default) 1: enable in this mode, the packet is looped back in the mac layer before going out of the chip. you must force linkup at full duplex as well. external loopback is another level of s ystem diagnostic which involves the phy device to loopback the packet. bits [4:3]: interface mode: 00 - gpsi mode 01 - mii mode 10 - reserved 11 - rmii mode (default) bit [5]: frame loopback. 0: disable frame from sending ba ck to its source port. (default) 1: allow frame to send back to its source port in a regular ethernet switch, a packet should never be receive and forwarded to the same port. setting the bit allows it to happen. this is not the same as an ingress mac loopback. the destination mac address has to be stored (learned) in the mct and as sociated with the originating source port. the frame loopback will only work for unicast packets. bit [6]: link heart beat receive 0: disable (default). also clears all mac lhb status. 1: enable bit [7]: soft reset. 0: normal operation (default) 1: reset. not self clearing. zl50410 data sheet 74 zarlink semiconductor inc. port 8: (cpu port) port 9: (gmac port) bits [1:0]: reserved bit [2]: enable special write to 2 registers in a single write operation. 0: disable (default) 1: enable should be enabled only in serial mode and disabled in 8/16-bit mode. bits [4:3]: enable insertion of 2-byte cpu info rmation in cpu frame packet in serial + mii mode 00: no information is inserted 01: insert 2-byte of cpu information 10: reserved 11: insert 6-byte of padding + 2- byte of cpu information (default) in port-based vlan mode, the cpu mii interface must be in ?no information is inserted? mode (ecr4p8[4:3]='00'). in tagged-based vlan mode, the cpu mii interface supports all three modes (0,2,8 bytes insertion). bit [5]: frame loopback. 0: disable frame from sending ba ck to its source port. (default) 1: allow frame to send back to its source port in a regular ethernet switch, a packet should never be receive and forwarded to the same port. setting the bit allows it to happen. this is not the same as an ingress mac loopback. the destination mac address has to be stored (learned) in the mct and as sociated with the originating source port. the frame loopback will only work for unicast packets. bit [6]: reserved bit [7]: soft reset. 0: normal operation (default) 1: reset. not self clearing. bit [0]: reserved bit [1]: enable rxclk output. active high 0: disable (default) 1: m9_rxclk pin becomes output in mii mode note: to configure port 9 with the devic e providing the interface clocks, you need to tie m9_rxclk to m9_mtxclk externally as m9_mtxclk is not a bidirectional clock. zl50410 data sheet 75 zarlink semiconductor inc. 12.3.1.5 buf_limit ? frame buffer limit cpu address:h036 accessed by cpu (r/w) 12.3.1.6 fcc ? flow control grant period cpu address:h037 accessed by cpu (r/w) bit [2]: internal loopback. 0: disable (default) 1: enable in this mode, the packet is looped back in the mac layer before going out of the chip. you must force linkup at full duplex as well. external loopback is another level of sy stem diagnostic which involves the phy device to loopback the packet. bits [4:3]: interface mode: 00 - mii mode 11 - gmii mode (default) bit [5]: frame loopback. 0: disable frame from sending bac k to its source port. (default) 1: allow frame to send back to its source port in a regular ethernet switch, a packet should never be receive and forwarded to the same port. setting the bit allows it to happen. this is not the same as an ingress mac loopback. the destination mac address has to be stored (learned) in the mct and associated with the originating source port. the frame loopback will onl y work for unicast packets. bit [6]: reserved bit [7]: soft reset. 0: normal operation (default) 1: reset. not self clearing. bits [6:0]: frame buffer limit (max 4 kb). multiple of 64 bytes (default 0x40) bit [7]: reserved bits [2:0]: flow control grant period (default 0x3) bits [7:3]: reserved zl50410 data sheet 76 zarlink semiconductor inc. 12.3.2 (group 1 address) vlan group 12.3.2.1 avtcl ? vlan type code register low i2c address 028; cpu address:h100 accessed by cpu and i2c (r/w) 12.3.2.2 avtch ? vlan type code register high i2c address 029; cpu address:h101 accessed by cpu and i2c (r/w) 12.3.2.3 pvmap00_0 ? port 0 configuration register 0 i2c address 02a, cpu address:h102 accessed by cpu and i2c (r/w) in port based vlan mode this register indicates the legal egress ports. a ?1? on bit 3 means that the packet can be sent to port 3. a ?0? on bit 3 means that any packet destined to port 3 will be discarded. this register works with registers 1 to form a 10 bit mask to all egress ports. in tag based vlan mode this is the default vlan tag. it works with configuration register pvmap00_1 [7:5] [3:0] to form a default vlan tag. if the received packet is untagged, then the packet is classi fied with the default vlan tag. if the received packet has a vlan id of 0, then pvid is used to replace the packet?s vlan id. 12.3.2.4 pvmap00_1 ? port 0 configuration register 1 i2c address h34, cpu address:h103 accessed by cpu and i2c (r/w) in port based vlan mode bits [7:0]: vlantype_low: lower 8 bits of the vlan type code (default 0x00) bits [7:0]: vlantype_high: upper 8 bits of the vlan type code (default is 0x81) bits [7:0]: vlan mask for port 0 (default 0xff) bits [7:0]: pvid [7:0] (default is 0xff) bits [1:0]: vlan mask for ports 9 to 8 (default 0x3) bits [7:2]: reserved (default 0x3f) zl50410 data sheet 77 zarlink semiconductor inc. in tag based vlan mode 12.3.2.5 pvmap00_3 ? port 0 configuration register 3 i2c address h3e, cpu address:h105 accessed by cpu and i2c (r/w) in port based vlan mode in tag-based vlan mode bits [3:0]: pvid [11:8] (default is 0xf) bit [4]: untrusted port. this register is used to change the vlan priority field of a packet to a predetermined priority. 1: vlan priority field is changed to bit [7:5] at ingres s port (default) 0: keep vlan priority field bits [7:5]: untag port priority (default 0x7) bits [2:0]: reserved bits [5:3]: default transmit priori ty. used when bit [7]=1 (default 0) transmit priority level 0 (lowest) transmit priority level 1 transmit priority level 2 transmit priority level 3 (highest) bit [6]: default discard priority. used when bit [7]=1 0 ? discard priority level 0 (lowest) (default) 1 ? discard priority level 1(highest) bit [7]: enable fix priority (default 0) 0 - disable. all frames are analysed. tr ansmit priority and discard priority are based on vlan tag, tos or logical port. 1 - enable. transmit priority and discard priority are based on values programmed in bit [6:3] bit [0]: not used bit [1]: ingress filter enable 0 - disable ingress filter. packets with vlan not belonging to source port are forwarded, if destination port belongs to the vlan. symmetric vlan. (default) 1 - enable ingress filter. packets with vlan not belonging to source port are filtered. asymmetric vlan. bit [2]: force untag out (vlan taggi ng is based on ieee 802.1q rule) . 0 - disable (default) 1 - force untagged output. all packets transmitted from this port are untagged. this bit is used when this port is c onnected to legacy equipment that does not support vlan tagging. zl50410 data sheet 78 zarlink semiconductor inc. 12.3.2.6 pvmapnn_0,1,3 ? ports 1~9 configuration registers pvmap01_0,1,3 i2c address h2b,35,3f; cpu address:h106,107,109 (port 1) pvmap02_0,1,3 i2c address h2c,36,40; cpu a ddress:h10a, 10b, 10d (port 2) pvmap03_0,1,3 i2c address h2d,37,41; cpu address:h10e, 10f, 111 (port 3) pvmap04_0,1,3 i2c address h2e,38,42; cpu a ddress:h112, 113, 115 (port 4) pvmap05_0,1,3 i2c address h2f,39,43; cpu a ddress:h116, 117, 119 (port 5) pvmap06_0,1,3 i2c address h30,3a,44; cpu address:h11a, 11b, 11d (port 6) pvmap07_0,1,3 i2c address h31,3b,45; cpu address:h11e, 11f, 121 (port 7) pvmap08_0,1,3 i2c address h32,3c,46; cpu addr ess:h122, 123, 125 (port cpu) pvmap09_0,1,3 i2c address h33,3d,47; cpu addr ess:h126, 127, 129 (port gmac) 12.3.2.7 pvmode i2c address: h048, cpu address:h170 accessed by cpu and i2c (r/w) bits [5:3]: default transmit priori ty. used when bit [7]=1 (default 0) transmit priority level 0 (lowest) transmit priority level 1 transmit priority level 2 transmit priority level 3 (highest) bit [6]: default discard priority. used when bit [7]=1 0 ? discard priority level 0 (lowest) (default) 1 ? discard priority level 1(highest) bit [7]: enable fix priority (default 0) 0 - disable. all frames are analysed. tr ansmit priority and discard priority are based on vlan tag, tos or logical port. 1 - enable. transmit priority and discard priority are based on values programmed in bit [6:3] bit [0]: vlan mode 0: port based vlan mode (default) 1: tag based vlan mode bit [1]: slow learning (default = 0) same function as se_opmode bit [7]. either bit can enable the function; both need to be turned off to disable the feature. bit [2]: disable dropping of frames with de stination mac addresses 01-80-c2-00-00-01 to 0x01-80-c2-00-00-0f. 0: drop all frames in this range (default) 1: disable dropping of frames in this range zl50410 data sheet 79 zarlink semiconductor inc. 12.3.3 (group 2 address) port trunking groups trunk group ? up to eight rmac ports can be selected for each trunk group. 12.3.3.1 trunk n? trunk group 0~7 cpu address:h200+n (n = trunk group) accessed by cpu (r/w) bit [7:0] port 7-0 bit map of trunk n. (default 0) bit [3]: flooding control in secure mode 0: enable - learning disabled port will not receive any flooding packets (default) 1: disable bit [4]: support mac address 0 0: mac address 0 is not learned. (default) this means packet with destination mac address 0 is forwarded as unknown destination. it is subjected to unicast to multicast rate control. 1: mac address 0 is learned. bit [5]: disable ieee multicast control frame (0 1-80-c2-00-00-00 to 01-80-c2-00-00-ff) to cpu in managed mode. in unmanaged mode, fr ame is forwarded as multicast (except pause frame). 0: frame is forwarded to cpu (default) 1: frame is forwarded as mu lticast (except pause frame) bit [6]: ip multicast enable 0: disable (default) 1: enable in general, this bit is equal to ^fen[4]. bit [7]: enable logical port match in secure mode 0: disable (default) 1: enable - when well known or user define logical port force discard enabled, force any ip packet with logical port number matching logical port numbers to cpu. b i t 7 b i t 0 trunk0 p o r t 7 p o r t 0 zl50410 data sheet 80 zarlink semiconductor inc. 12.3.3.2 trunkn_hash10 ? trunk group n hash result 1/0 destination port number cpu address:h208+4n (n = trunk group) accessed by cpu (r/w) 12.3.3.3 trunkn_hash32 ? trunk group n ha sh result 3/2 destination port number cpu address:h209+4n (n = trunk group) accessed by cpu (r/w) 12.3.3.4 trunkn_hash54 ? trunk group n hash result 5/4 destination port number cpu address:h20a+4n (n = trunk group) accessed by cpu (r/w) 12.3.3.5 trunkn_hash76 ? trunk group n hash result 7/6 destination port number cpu address:h20b+4n (n = trunk group) accessed by cpu (r/w) bits [3:0] hash result 0 destina tion port number (default 0) bits [7:4] hash result 1 destina tion port number (default 0) bits [3:0] hash result 2 destina tion port number (default 0) bits [7:4] hash result 3 destina tion port number (default 0) bits [3:0] hash result 4 destina tion port number (default 0) bits [7:4] hash result 5 destina tion port number (default 0) bits [3:0] hash result 6 destina tion port number (default 0) bits [7:4] hash result 7 destina tion port number (default 0) zl50410 data sheet 81 zarlink semiconductor inc. 12.3.3.6 pvlan_pn ? per-port private vlan edge (protected ports) cpu address:h220+n (n = rmac port number) accessed by cpu (r/w) only applicable if private vlan e dge feature is enable (fen[1]=?1?). note: these registers over lap trunk6/7_hashxy registers, thus, trunk group s 6 and 7 must be disabled (trunk6=trunk7=0x00) if the pvlan feature is enabled. multicast hash registers multicast hash registers are used to distribute multicast tr affic. 16 registers are used to form a 8-entry array; each entry has 10 bits, with each bit repr esenting one port. any port not be longing to a trunk group should be programmed with 1. ports belonging to the same trunk grou p should only have a single port set to ?1? per entry. the port set to ?1? is picked to transmit the multicast frame when the hash value is met. 12.3.3.7 multicast_hashn-0 ? mult icast hash result 0~7 mask byte 0 cpu address:h228+2n (n = hash value) accessed by cpu (r/w) bits [7:0] port 9,7-0 bit map of protected port n (default 0x00) bits [7:0] represent ports 9,7-0, ex cluding the source port. for example: for port 0, [7:0] represent ports 9,7..1 for port 1, [7:0] represent ports 9,7..2,0 for port 2, [7:0] represent ports 9,7..3,1..0 hash value =0 hash0-1 hash0-0 hash value =1 hash1-1 hash1-0 hash value =2 hash2-1 hash2-0 hash value =3 hash3-1 hash3-0 hash value =4 hash4-1 hash4-0 hash value =5 hash5-1 hash5-0 hash value =6 hash6-1 hash6-0 hash value =7 hash7-1 hash7-0 p o r t 9 p o r t 8 p o r t 7 p o r t 0 bits [7:0]: port 7-0 bit map fo r multicast hash. (default 0xff) zl50410 data sheet 82 zarlink semiconductor inc. 12.3.3.8 multicast_hashn-1 ? mult icast hash result 0~7 mask byte 1 cpu address:h229+2n (n = hash value) accessed by cpu (r/w) 12.3.4 (group 3 address) cpu port configuration group mac5 to mac0 registers form the cpu mac address. when a packet with destination mac address match mac [5:0], the packet is forwarded to the cpu. the default mac address is 00-00-00-00-00-00. 12.3.4.1 mac0 ? cpu mac address byte 0 cpu address:h300 accessed by cpu (r/w) bits [1:0]: port 9-8 bit map fo r multicast hash. (default 0x3) bit [2]: multicast_hash1-1 unknown ip multicast filter enable 1: enable (default) 0: disable if this feature is enabl ed, unknown ip multicast pa ckets or unknown multicast packets can be either filtered or sent to the cpu, based on bits [13:12] in the per vlan port association table. this feature is only applicable in tagged-based vlan mode (pvmode[0]=?1?). in port-based vlan mode (pvmode[0]=?0?), this bit is ignored. multicast_hash[7:2,0]-1 reserved (default 0x1) bits [5:3]: reserved (default 0x7) bits [7:6]: multicast_hash0-1 hash select. the hash algorithm selected is valid for all trunks 00 - use source and destination mac address for hashing 01 - use source mac address for hashing 10 - use destination mac address for hashing 11 - use source port number for hashing (default) multicast_hash[7:1]-1 reserved (default 0x3) 47 0 (mc bit) mac5 mac4 mac3 mac2 mac1 mac0 bits [7:0]: byte 0 (bits [7:0]) of the cpu mac address (default 0) zl50410 data sheet 83 zarlink semiconductor inc. 12.3.4.2 mac1 ? cpu mac address byte 1 cpu address:h301 accessed by cpu (r/w) 12.3.4.3 mac2 ? cp u mac address byte 2 cpu address:h302 accessed by cpu (r/w) 12.3.4.4 mac3 ? cp u mac address byte 3 cpu address:h303 accessed by cpu (r/w) 12.3.4.5 mac4 ? cp u mac address byte 4 cpu address:h304 accessed by cpu (r/w) 12.3.4.6 mac5 ? cp u mac address byte 5 cpu address:h305 accessed by cpu (r/w) 12.3.4.7 int_mask0 ? interrupt mask cpu address:h306 accessed by cpu (r/w) the cpu can dynamically mask the interrupt when it is busy and doesn?t want to be interrupted. (default 0x00) - 1: mask the interrupt - 0: unmask the interrupt (e nable interrupt) (default) bits [7:0]: byte 1 (bits [15:8]) of the cpu mac address (default 0) bits [7:0]: byte 2 (bits [23:16]) of the cpu mac address (default 0) bits [7:0]: byte 3 (bits [31:24]) of the cpu mac address (default 0) bits [7:0]: byte 4 (bits [39:32]) of the cpu mac address (default 0) bits [7:0]: byte 5 (bits [47:40]) of the cpu mac address (default 0) note: bits [42:40] are set on a per por t basis using mac01, mac23, mac45, mac67 registers. for port 9, this regi ster is ignored and mac9 is used for bits [47:40]. zl50410 data sheet 84 zarlink semiconductor inc. 12.3.4.8 intp_mask0 ? interrupt mask for mac port 0,1 cpu address:h310 accessed by cpu (r/w) the cpu can dynamically mask the interrupt when it is busy and doesn?t want to be interrupted (default 0x00) - 1: mask the interrupt - 0: unmask the interrupt (default) 12.3.4.9 intp_maskn ? interrupt mask for mac ports 2~9 registers intp_mask1 cpu address:h311 (ports 2,3) intp_mask2 cpu address:h312 (ports 4,5) intp_mask3 cpu address:h313 (ports 6,7) intp_mask4 cpu address:h314 (port cpu,gmac) 12.3.4.10 rqs ? receive queue select cpu address:h323 accessed by cpu (rw) select which receive queue is being used by the cpu port. note: strict priority applies between different sele cted queues (uq3>uq2>uq1>uq0>mq3>mq2>mq1>mq0). bit [0]: cpu frame interrupt. cpu fr ame buffer has data for cpu to read bit [1]: control command 1 interrupt. control command frame buffer1 has data for cpu to read bit [2]: control command 2 interrupt. control command frame buffer2 has data for cpu to read bits [6:3]: reserved bit [7]: device timeout detected interrupt bit [0]: port 0 statistic counter wrap around interrupt mask. an interrupt is generated when a statistic counter wraps around. refer to hardware statistic counter for interrupt sources bit [1]: port 0 link change mask bit [2]: port 0 module detect mask bit [3]: reserved bit [4]: port 1 statistic counter wrap around interrupt mask. an interrupt is generated when a statistic counter wraps around. refer to hardware statistic counter for interrupt sources. bit [5]: port 1 link change mask bit [6]: port 1 module detect mask bit [7] reserved zl50410 data sheet 85 zarlink semiconductor inc. 12.3.4.11 rqss ? receive queue status cpu address:h324 accessed by cpu (ro) cpu receive queue status 12.3.4.12 mac01 ? increment mac port 0,1 address cpu address:h325 accessed by cpu (rw) mac01, mac23, mac45, mac67, and mac9 registers are used with the mac0~5 registers to form the cpu mac address on a per port basis. 12.3.4.13 mac23 ? increment mac port 2,3 address cpu address:h326 accessed by cpu (rw) bit [0]: select queue 0 0: not selected (default) 1: selected bit [1]: select queue 1 bit [2]: select queue 2 bit [3]: select queue 3 bit [4]: select multicast queue 0 bit [5]: select multicast queue 1 bit [6]: select multicast queue 2 bit [7]: select multicast queue 3 bits [3:0]: unicast queue 3 to 0 not empty 0: empty 1: not empty bits [7:4]: multicast queue 3 to 0 not empty bits [2:0]: bits [42:40] of port 0 cpu mac address bit [3]: reserved bits [6:4]: bits [42:40] of port 1 cpu mac address bit [7]: reserved bits [2:0]: bits [42:40] of port 2 cpu mac address bit [3]: reserved zl50410 data sheet 86 zarlink semiconductor inc. 12.3.4.14 mac45 ? increment mac port 4,5 address cpu address:h327 accessed by cpu (rw) 12.3.4.15 mac67 ? increment mac port 6,7 address cpu address:h328 accessed by cpu (rw) 12.3.4.16 mac9 ? increment mac port 9 address cpu address:h329 accessed by cpu (rw) 12.3.4.17 cpuqins0 - cpuqins6 ? cpu queue insertion command cpu address:h330-336 accessed by cpu, (r/w) bits [6:4]: bits [42:40] of port 3 cpu mac address bit [7]: reserved bits [2:0]: bits [42:40] of port 4 cpu mac address bit [3]: reserved bits [6:4]: bits [42:40] of port 5 cpu mac address bit [7]: reserved bits [2:0]: bits [42:40] of port 6 cpu mac address bit [3]: reserved bits [6:4]: bits [42:40] of port 7 cpu mac address bit [7]: reserved bits [7:0]: bits [47:40] of port 9 cpu mac address 55 0 cq6 cq5 cq4 cq3 cq2 cq1 cq0 zl50410 data sheet 87 zarlink semiconductor inc. cpu queue insertion command 12.3.4.18 cpuqinsrpt ? cpu queue insertion report cpu address:h337 accessed by cpu, (ro) cpu command queue status 12.3.4.19 cpugrnhdl0 - cpugrnhdl 1 ? cpu allocated granule pointer cpu address:h338-339 accessed by cpu, (ro) cpu queue insertion command 12.3.4.20 cpurlsinfo0 - cpurlsinfo4 ? receive queue status cpu address:h33a-33e accessed by cpu, (r/w) bits [9:0]: destination ma p (gmac, cpu, port 7-0). bits [13:10] priority bits [20:14] number of granules for the frame bits [35:21] tail pointer bits [50:36] header pointer bit [51] multicast frame (has to be one if more than one destination port) bits [54:52] reserved bit [55] command valid (will be processe d on the rising edge of the signal) bit [0]: the command is under processing. bit [1]: insertion fail (may be due to queue full, wred or filtering) 15 0 cg1 cg0 bits [14:0]: granule pointer. bit [15]: pointer valid 0 cr4 cr3 cr2 cr1 cr0 zl50410 data sheet 88 zarlink semiconductor inc. cpu queue insertion command 12.3.4.21 cpugrnct r ? cpu granule control cpu address:h33f accessed by cpu, (r/w) cpu receive queue status 12.3.5 (group 4 address) search engine group 12.3.5.1 agetime_low ? mac address aging time low i2c address h049; cpu address:h400 accessed by cpu and i2c (r/w) used in conjuction with agetime_high. the zl50410 remo ves the mac address from the data base and sends a delete mac address control command to the cpu. 12.3.5.2 agetime_high ?mac address aging time high i2c address h04a; cpu address h401 accessed by cpu and i2c (r/w) the default setting of agetime_low/ high provides 300 seconds aging time. aging time is based on the following equation: {agetime_high,agetime_low} x (# of mac entries in the memory x 800 sec). number of mac entries = 4 k. bits [14:0]: header pointer bits [30:15] tail pointer bits [38:32] number of granules for the release bit [0]: allocate granule to the cpu if set to one. otherwise, do not allocate any resource. bit [1]: read allocated granule (at rising edge only) bit [2]: release info valid (will be processed at rising edge only) bits [7:0]: low byte of the mac address aging timer (default 0x5c) bits [7:0]: high byte of the mac address aging timer (default 0x00) zl50410 data sheet 89 zarlink semiconductor inc. 12.3.5.3 se_opmode ? search engine operation mode cpu address:h403 accessed by cpu (r/w) note: ecr2[2] enable/disable learning for each port. 12.3.6 (group 5 address) buffer control/qos group 12.3.6.1 qosc ? qos control i2c address h04b; cpu address:h500 accessed by cpu and i 2 c (r/w) bit [0]: reserved. must be 0. bit [1]: protocol filtering mode 0 ? inclusive (default) 1 ? exclusive bit [2]: delete mac report control 0 ? report mac address deletion (mac address is deleted from mct after aging time) (default) 1 ? disable report mac address deletion bit [3]: delete control 0 ? mac address entry is removed when it is old enough to be aged (default) 1 ? disable aging logic from removing mac during aging however, a report is still sent to the cpu in both cases, when bit [2] = 0 bit [4]: enable rsvp packet trapping 0 - disable rsvp packet trapping. (default) 1 - enable rsvp packet trapping. ip multicast also needs to be enabled for this function. bit [5] arp report control 0 - no arp packet reporting (default) 1 - report arp packet to cpu bit [6]: disable mct speed-up aging 0 ? enable speed-up aging when mct resource is low. (default) 1 ? disable speed-up aging when mct resource is low. bit [7]: slow learning 0 ? learning is performed independent of search demand (default) 1 ? enable slow learning. learning is temporary disabled when search demand is high bit [0]: enable tx rate control (on rmac ports only) 0 ? disable (default) 1 ? enable zl50410 data sheet 90 zarlink semiconductor inc. 12.3.6.2 ucc ? unicast congestion control i 2 c address h068, cpu address: 510 accessed by cpu and i 2 c (r/w) 12.3.6.3 mcc ? multicast congestion control i2c address h069, cpu address: 511 accessed by cpu and i2c (r/w) 12.3.6.4 mccth ? multicast threshold control cpu address: 512 accessed by cpu (r/w) bit [1]: enable rx rate control (on rmac ports only) 0 ? disable (default) 1 ? enable bits [4:2]: reserved bit [5]: select vlan tag or tos (ip pa ckets) to be preferentially picked to map transmit priority and drop priority 0 ? select vlan tag priority field over tos (default) 1 ? select tos over vlan tag priority field bit [6]: select tos bits for priority 0 ? use tos [4:2] bits to map the transmit priority (default) 1 ? use tos [7:5] bits to map the transmit priority bit [7]: select tos bits for drop priority 0 ? use tos [4:2] bits to map the drop priority (default) 1 ? use tos [7:5] bits to map the drop priority bits [7:0]: number of frame count. used for best ef fort dropping at b% when destination port?s best effort queue reaches ucc thresh old and shared pool is all in use. granularity is 16 granule (default 0x6) bits [7:0]: in multiples of 16 granules (granularity) . used for triggering mc flow control when destination port?s multicast best effort queue reaches mcc threshold. (default 0x6) bits [7:0]: threshold on the multicast granule count . exceeding the threshold consider as multicast resource low and the new multicast will be dropped at b% or flow con- trol is triggered if enabled. (default: 0x3) zl50410 data sheet 91 zarlink semiconductor inc. 12.3.6.5 rdrc0 ? wred rate control 0 i2c address 090, cpu address 513 accessed by cpu and i 2 c (r/w) 12.3.6.6 rdrc1 ? wred rate control 1 i2c address 091, cpu address 514 accessed by cpu and i2c (r/w) 12.3.6.7 rdrc2 ? wred rate control 2 cpu address 515 accessed by cpu (r/w) 12.3.6.8 sfcb ? share fcb size i2c address h074, cpu address 518 accessed by cpu and i2c (r/w) bits [3:0]: corresponds to the frame drop per centage y% for wred. granularity 6.25%. bits [7:4]: corresponds to the frame drop per centage x% for wred. granularity 6.25%. see programming qos registers application note, zlan-42, for more information bits [3:0]: corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. granularity 6.25%. bits [7:4]: corresponds to the frame drop percentage z% for wred. granularity 6.25%. see programming qos registers application note, zlan-42, for more information bits [3:0]: corresponds to the frame drop percentage rb% for ingress rate control. granularity 6.25%. bits [7:4]: corresponds to the frame drop percentage ra% for ingress rate control. granularity 6.25%. bits [7:0]: expressed in multiples of 16 granules. buffer reservation for shared pool. zl50410 data sheet 92 zarlink semiconductor inc. 12.3.6.9 c1rs ? class 1 reserve size i2c address h075, cpu address 519 accessed by cpu and i2c (r/w) buffer reservation for class 1. granularity 16 granules . (default 0) 12.3.6.10 c2rs ? class 2 reserve size i2c address h076, cpu address 51a accessed by cpu and i2c (r/w) buffer reservation for class 2. granularity 16 granules . (default 0) 12.3.6.11 c3rs ? class 3 reserve size i2c address h077, cpu address 51b accessed by cpu and i2c (r/w) buffer reservation for class 3. granularity 16 granules . (default 0) 12.3.6.12 avpml ? vlan tag priority map i2c address h056; cpu address:h530 accessed by cpu and i2c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan t ag priorities to map into ei ght internal level transmit priorities. under the internal transmit pr iority, seven is the highest priority wher e as zero is the lowest. this feature allows the user the flexibility of redefi ning the vlan priority field. for exampl e, programming a value of 7 into bit 2:0 of the avpml register would map packet vlan priority 0 in to internal transmit priority 7. the new priority is used inside the zl50410. when the packet goes out it carries the original priority. bits [7:0]: class 1 fcb reservation bits [7:0]: class 2 fcb reservation bits [7:0]: class 3 fcb reservation bits [2:0]: priority when the vlan tag priority field is 0 (default 0) bits [5:3]: priority when the vlan tag priority field is 1 (default 0) bits [7:6]: priority when the vlan tag priority field is 2 (default 0) zl50410 data sheet 93 zarlink semiconductor inc. 12.3.6.13 avpmm ? vlan priority map i2c address h057, cpu address:h531 accessed by cpu and i2c (r/w) map vlan priority into eight level transmit priorities: 12.3.6.14 avpmh ? vlan priority map i2c address h058, cpu address:h532 accessed by cpu and i2c (r/w) map vlan priority into eight level transmit priorities: 12.3.6.15 avdm ? vlan discard map i2c address h05c, cpu address:h533 accessed by cpu and i2c (r/w) map vlan priority into frame discard when lo w priority buffer usage is above threshold bit [0]: priority when the vlan tag priority field is 2 (default 0) bits [3:1]: priority when the vlan tag priority field is 3 (default 0) bits [6:4]: priority when the vlan tag priority field is 4 (default 0) bit [7]: priority when the vlan tag priority field is 5 (default 0) bits [1:0]: priority when the vlan tag priority field is 5 (default 0) bits [4:2]: priority when the vlan tag priority field is 6 (default 0) bits [7:5]: priority when the vlan tag priority field is 7 (default 0) bit [0]: frame drop priority when vlan t ag priority field is 0 (default 0) bit [1]: frame drop priority when vlan t ag priority field is 1 (default 0) bit [2]: frame drop priority when vlan t ag priority field is 2 (default 0) bit [3]: frame drop priority when vlan t ag priority field is 3 (default 0) bit [4]: frame drop priority when vlan t ag priority field is 4 (default 0) bit [5]: frame drop priority when vlan t ag priority field is 5 (default 0) bit [6]: frame drop priority when vlan t ag priority field is 6 (default 0) bit [7]: frame drop priority when vlan t ag priority field is 7 (default 0) zl50410 data sheet 94 zarlink semiconductor inc. 12.3.6.16 tospml ? tos priority map i2c address h059, cpu address:h540 accessed by cpu and i2c (r/w) map tos field in ip packet into eight level transmit priorities 12.3.6.17 tospmm ? tos priority map i2c address h05a, cpu address:h541 accessed by cpu and i2c (r/w) map tos field in ip packet into eight level transmit priorities 12.3.6.18 tospmh ? tos priority map i2c address h05b, cpu address:h542 accessed by cpu and i2c (r/w) map tos field in ip packet into eight level transmit priorities: 12.3.6.19 tosdml ? tos discard map i2c address h05d, cpu address:h543 accessed by cpu and i2c (r/w) map tos into frame discard when low prio rity buffer usage is above threshold bits [2:0]: priority when the tos field is 0 (default 0) bits [5:3]: priority when the tos field is 1 (default 0) bits [7:6]: priority when the tos field is 2 (default 0) bit [0]: priority when the tos field is 2 (default 0) bits [3:1]: priority when the tos field is 3 (default 0) bits [6:4]: priority when the tos field is 4 (default 0) bit [7]: priority when the tos field is 5 (default 0) bits [1:0]: priority when the tos field is 5 (default 0) bits [4:2]: priority when the tos field is 6 (default 0) bits [7:5]: priority when the tos field is 7 (default 0) bit [0]: frame drop priority when tos field is 0 (default 0) bit [1]: frame drop priority when tos field is 1 (default 0) bit [2]: frame drop priority when tos field is 2 (default 0) zl50410 data sheet 95 zarlink semiconductor inc. 12.3.6.20 user_protocol_n ? user define protocol 0~7 i2c address h0b3+n, cpu address:h550+n accessed by cpu and i2c (r/w) (default 00) this register is duplic ated eight times from protocol 0~7 and allows the cpu to define eight separate protocols. 12.3.6.21 user_protocol_force_discard ? user define protocol 0~7 force discard i2c address h0bb, cpu address 558 accessed by cpu and i2c (r/w) user defined logical ports and well known ports the zl50410 supports classifying packet priority through laye r 4 logical port information. it can be setup by 8 well known ports, 8 user defined logical ports, and 1 user defined range. the 8 well known ports supported are: ?23 ?512 ?6000 ?443 ? 111 bit [3]: frame drop priority when tos field is 3 (default 0) bit [4]: frame drop priority when tos field is 4 (default 0) bit [5]: frame drop priority when tos field is 5 (default 0) bit [6]: frame drop priority when tos field is 6 (default 0) bit [7]: frame drop priority when tos field is 7 (default 0) bits [7:0]: user define protocol bit [0]: enable protocol 0 force discard 1 ? enable 0 ? disable bit [1]: enable protocol 1 force discard bit [2]: enable protocol 2 force discard bit [3]: enable protocol 3 force discard bit [4]: enable protocol 4 force discard bit [5]: enable protocol 5 force discard bit [6]: enable protocol 6 force discard bit [7]: enable protocol 7 force discard zl50410 data sheet 96 zarlink semiconductor inc. ? 22555 ?22 ?554 their respective priority c an be programmed via well_known_port[7:0]_priority register. well_known_port[_enable can individually tu rn on/off each well known port if desired. similarly, the user defined logical port pr ovides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. the 8 user logical port s can be programmed via user_port 0-7 registers. two registers are required to be programmed for the logical port number. the respective priority can be programmed to the user_port [7:0] priori ty register. the port priority can be individually enabled/disabled via user_port_enable register. the user defined range provides a range of logical port numbers with the same priority level. programming is similar to the user defined logical port. instead of pr ogramming a fixed port number, an upper and lower limit need to be programmed, they are: {rhighh, rhighl} and {rlo wh, rlowl} respectively. if the value in the upper limit is smaller or equal to the lower limit, the function is dis abled. any ip packet with a l ogical port that is less than the upper limit and more than the lower limit will use the priority spec ified in rpriority. 12.3.6.22 well_known_port[1:0]_priority- well known logic port 1 and 0 priority i2c address h0a8, cpu address 560 accessed by cpu and i2c (r/w) 12.3.6.23 well_known_port[3:2]_priority- well known logic port 3 and 2 priority i2c address h0a9, cpu address 561 accessed by cpu and i2c (r/w) 12.3.6.24 well_known_port[5:4]_priority- well known logic port 5 and 4 priority i2c address h0aa, cpu address 562 accessed by cpu and i2c (r/w) bits [3:0]: priority setting, transmission + dropping, for well known port 0 (23 for telnet) bits [7:4]: priority setting, transmission + dr opping, for well known port 1 (512 for tcp/udp) bits [3:0]: priority setting, transmission + dropping, for well known port 2 (6000 for xwin) bits [7:4]: priority setting, transmission + dropping, for well known port 3 (443 for http sec) bits [3:0]: priority setting, transmission + dropping, for well known port 4 (111 for sun remote procedure call) bits [7:4]: priority setting, transmission + dropping, for well known port 5 (22555 for ip phone call setup) zl50410 data sheet 97 zarlink semiconductor inc. 12.3.6.25 well_known_port[7:6]_priority- well known logic port 7 and 6 priority i2c address h0ab, cpu address 563 accessed by cpu and i2c (r/w) 12.3.6.26 well_known_port_enable ? well known logic port 0 to 7 enables i2c address h0ac, cpu address 564 accessed by cpu and i2c (r/w) 12.3.6.27 well_known _port_force_discard ? well kn own logic port 0~7 force discard i2c address h0ad, cpu address 565 accessed by cpu and i2c (r/w) bits [3:0]: priority setting, transmission + dropping, for well known port 6 (22 for ssh) bits [7:4]: priority setting, transmission + dropping, for well known port 7 (554 for rtsp) bit [0]: enable well known port 0 priority 1 ? enable 0 ? disable bit [1]: enable well known port 1 priority bit [2]: enable well known port 2 priority bit [3]: enable well known port 3 priority bit [4]: enable well known port 4 priority bit [5]: enable well known port 5 priority bit [6]: enable well known port 6 priority bit [7]: enable well known port 7 priority bit [0]: enable well known port 0 force discard 1 ? enable 0 ? disable bit [1]: enable well known port 1 force discard bit [2]: enable well known port 2 force discard bit [3]: enable well known port 3 force discard bit [4]: enable well known port 4 force discard bit [5]: enable well known port 5 force discard bit [6]: enable well known port 6 force discard bit [7]: enable well known port 7 force discard zl50410 data sheet 98 zarlink semiconductor inc. 12.3.6.28 user_port[7:0]_[lowithhigh] ? user define logical port 0~7 i2c address h092+n(low); cpu address 570+2n(low) (n = logical port number) i2c address h09a+n(high); cpu address 571+2n(high) accessed by cpu and i2c (r/w) (default 00) this register is duplicated eight times fr om port 0 through port 7 and allows the cpu to define eight separate ports. 12.3.6.29 user_port_[1:0]_priority - user define logic port 1 and 0 priority i2c address h0a2, cpu address 590 accessed by cpu and i2c (r/w) the chip allows the cpu to define the priority 12.3.6.30 user_port_[3:2]_priority - user define logic port 3 and 2 priority i2c address h0a3, cpu address 591 accessed by cpu and i2c (r/w) 12.3.6.31 user_port_[5:4]_priority - user define logic port 5 and 4 priority i2c address h0a4, cpu address 592 accessed by cpu and i2c (r/w) 70 tcp/udp logic port low 70 tcp/udp logic port high bits [3:0]: priority setting, transmission + dropping, for logic port 0 bits [7:4]: priority setting, transmission + dr opping, for logic port 1 (default 00) bits [3:0]: priority setting, transmission + dropping, for logic port 2 bits [7:4]: priority setting, transmission + dr opping, for logic port 3 (default 00) bits [3:0]: priority setting, transmission + dropping, for logic port 4 bits [7:4]: priority setting, transmission + dr opping, for logic port 5 (default 00) zl50410 data sheet 99 zarlink semiconductor inc. 12.3.6.32 user_port_[7:6]_priority - user define logic port 7 and 6 priority i2c address h0a5, cpu address 593 accessed by cpu and i2c (r/w) 12.3.6.33 user_port_enable[7:0] ? user define logic port 0 to 7 enables i2c address h0a6, cpu address 594 accessed by cpu and i2c (r/w) 12.3.6.34 user_port_force_discard[7:0] ? user define logic port 0~7 force discard i2c address h0a7, cpu address 595 accessed by cpu and i2c (r/w) bits [3:0]: priority setting, transmission + dropping, for logic port 6 bits [7:4]: priority setting, transmission + dr opping, for logic port 7 (default 00) bit [0]: enable user port 0 priority 1 ? enable 0 ? disable bit [1]: enable user port 1 priority bit [2]: enable user port 2 priority bit [3]: enable user port 3 priority bit [4]: enable user port 4 priority bit [5]: enable user port 5 priority bit [6]: enable user port 6 priority bit [7]: enable user port 7 priority bit [0]: enable user port 0 force discard 1 ? enable 0 ? disable bit [1]: enable user port 1 force discard bit [2]: enable user port 2 force discard bit [3]: enable user port 3 force discard bit [4]: enable user port 4 force discard bit [5]: enable user port 5 force discard bit [6]: enable user port 6 force discard bit [7]: enable user port 7 force discard zl50410 data sheet 100 zarlink semiconductor inc. 12.3.6.35 rlowl ? user define range low bit 7:0 i2c address h0ae, cpu address: 5a0 accessed by cpu and i2c (r/w) 12.3.6.36 rlowh ? user define range low bit 15:8 i2c address h0af, cpu address: 5a1 accessed by cpu and i2c (r/w) 12.3.6.37 rhighl ? user de fine range high bit 7:0 i2c address h0b0, cpu address: 5a2 accessed by cpu and i2c (r/w) 12.3.6.38 rhighh ? user define range high bit 15:8 i2c address h0b1, cpu address: 5a3 accessed by cpu and i2c (r/w) 12.3.6.39 rpriority ? user define range priority i2c address h0b2, cpu address: 5a4 accessed by cpu and i2c (r/w) rlow and rhigh form a range for logical ports to be classified with priority specified in rpriority. bits [7:0]: lower 8 bit of the user define logical port low range bits [7:0]: upper 8 bit of the user define logical port low range bits [7:0]: lower 8 bit of the user define logical port high range bits [7:0]: upper 8 bit of the user define logical port high range bit [0]: drop priority (inclusive only) bits [3:1] transmit priority (inclusive only) bits [5:4] reserved bits [7:6] 00 - no filtering 01 - exclusive filtering (x<=rlow or x>=rhigh) 10 - inclusive filtering (rlow zl50410 data sheet 102 zarlink semiconductor inc. 12.3.7.4 miic0 ? mii command register 0 cpu address:h603 accessed by cpu (r/w) bit [1]: private vlan edge support 0: disable (default) 1: enable if this feature is enabled, use regi sters pvlan_pn to set up the egress protected port map. this feature is only applicable in tagged-based vlan mode (pvmode[0]=?1?). in port-based vlan mode (pvmode[0]=?0?), this bit must be 0. see private vlan edge application note, zlan-130, for more information. bit [2]: support ds ef code. 0 ? disable (default) 1 ? enable (all ports) when 101110 is detected in ds field (t os[7:2]), the frame priority is set for 110 and drop is set for 0. bit [3]: enable vlan id hashing 0 ? disable (default) 1 ? enable bit [4]: disable ip multicast suppor t 0 ? enable ip multicast support (must also set pvmode[6]=1) 1 ? disable ip multicast support (default) when enable, igmp packets are identified by search engine and are passed to the cpu for processing. ip multicast packets are forwarded to the ip multicast group members according to the vlan port mapping table. bit [5]: report to cpu 0 ? disable (default) 1 ? enable when disable new vlan port associat ion report, new mac address report or aging reports are disable for all ports . when enable, register se_opmode is used to enable/disable se lectively eac h function. bit [6]: mii management state machine 0: enable (default) 1: disable this bit must be set so that there is no contention on the mdio bus between mii management state machine and mi ic & miid phy register accesses. bit [7]: mct link list structure 0 ? enable (default) 1 ? disable bits [7:0]: mii command data [7:0] zl50410 data sheet 103 zarlink semiconductor inc. note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 12.3.7.5 miic1 ? mii command register 1 cpu address:h604 accessed by cpu (r/w) note : before programming mii command: set fen[6], c heck miic3, making sure no rdy and no valid; then program mii command. 12.3.7.6 miic2 ? mii command register 2 cpu address:h605 accessed by cpu (r/w) note : before programming mii command: set fen[6], c heck miic3, making sure no rdy and no valid; then program mii command. 12.3.7.7 miic3 ? mii command register 3 cpu address:h606 accessed by cpu (r/w) note : before programming mii command: set fen[6], c heck miic3, making sure no rdy and no valid; then program mii command. writing this register will init iate a serial management cycle to the mii management interface. 12.3.7.8 miid0 ? mii data register 0 cpu address:h607 accessed by cpu (ro) bits [7:0]: mii command data [15:8] bits [4:0] reg_ad ? register phy address bits [6:5] op ? operation code ?10? for read command and ?01? for write command bits [7] reserved bits [4:0] phy_ad ? 5 bit phy address bit [5] reserved bit [6] valid ? data valid from phy (read only) bit [7] rdy ? data is returned from phy (read only) bits [7:0]: mii data [7:0] zl50410 data sheet 104 zarlink semiconductor inc. 12.3.7.9 miid1 ? mii data register 1 cpu address:h608 accessed by cpu (ro) 12.3.7.10 usd ? one micro second divider cpu address:h609 accessed by cpu (r/w) 12.3.7.11 device mode cpu address:h60a accessed by cpu (r/w) 12.3.7.12 checksum - eeprom checksum i2c address 0ff, cpu address:h60b accessed by cpu and i2c (r/w) this register is used in unmanaged mode only. before requesting that the zl50410 u pdates the eeprom device, the correct checksum needs to be calculated and written into this checksum register. bits [7:0]: mii data [15:8] bits [5:0]: divider to get one micro second from m_clk (only used when not in standard rmii mode) in a mii or gpsi system, a 50mhz m_clk may not be available. t he system designer can decide to use another frequency on the m_clk signal. to compensate for this, this register is required to be programmed. for example. if 20mhz is used on m_clk, to compensate for the difference, this register is programmed with 20 to provide 1usec for internal reference. bits [7:6]: reserved bit [0]: reserved bit [1]: cpu interrupt polarity 0: negative polarity 1: positive polarity (default) bits [4:2]: reserved bits [7:5]: device id (default 0). this is for stacking operation. this is the stack id for loop topology. bits [7:0]: checksum content (default 0) zl50410 data sheet 105 zarlink semiconductor inc. the checksum formula is: ff i2c register = 0 i = 0 when the zl50410 boots from the eeprom the checksum is calculated and the value must be zero. if the checksum is not zeroed the zl50410 does not start and pin checksum_ok is set to zero. 12.3.7.13 lhbtimer ? link heart beat timeout timer cpu address:h610 accessed by cpu (r/w) in slot time (512 bit time). lhb packet will be sent out to the remote device if no other packet is transmitted in half this period. the receiver will tri gger lhb timeout interrupt if not rece iving any good packet in this period. 12.3.7.14 lhbreg0, lhbreg1 - link heart beat opcode cpu address:h611, h612 accessed by cpu (r/w) the lhb frame uses mac control frame format (same as flow control frame.) the register here defines the operation code (we recommend h00-12). 12.3.7.15 fmaccreg0, fmaccreg1 - mac control frame opcode cpu address:h613, h614 accessed by cpu (r/w) the registers define the operation code if ma c control frame is fo rced out by processor. 12.3.7.16 fcb base address register 0 i2c address 0bf, cpu address:h620 accessed by cpu and i2c (r/w) 12.3.7.17 fcb base address register 1 i2c address 0c0, cpu address:h621 accessed by cpu and i2c (r/w) bits [7:0] fcb base address bit 7:0 (default 0) bits [7:0] fcb base address bit 15:8 (default 0x60) zl50410 data sheet 106 zarlink semiconductor inc. 12.3.7.18 fcb base address register 2 i2c address 0c1, cpu address:h622 accessed by cpu and i2c (r/w) 12.3.8 (group 7 address) port mirroring group 12.3.8.1 mirror control ? port mirror control register cpu address 70c accessed by cpu (r/w) (default 00) 12.3.8.2 mirror_dest_mac[5:0] ? mirror destination mac address 0~5 cpu address 700-705 accessed by cpu (r/w) 12.3.8.3 mirror_src _mac[5:0] ? mirror source mac address 0~5 cpu address 706-70b accessed by cpu (r/w) bits [7:0] fcb base address bit 23:16 (default 0) bits [3:0]: destination port to be mirrored to. bit [4] mirror flow from mirror_src_mac[5:0] to mirror_dest_mac[5:0] bit [5] mirror flow from mirror_d est_mac[5:0] to mi rror_src_mac[5:0] bit [6]: mirror when address is destination bit [7]: mirror when address is source dest_mac5 dest_mac4 dest_mac3 dest_mac2 dest_mac1 dest_mac0 [47:40] (default 00) [39:32] (default 00) [31:24] (default 00) [23:16] (default 00) [15:8] (default 00) [7:0] (default 00) src_mac5 src_mac4 src_mac3 src_mac2 src_mac1 src_mac0 [47:40] (default 00) [39:32] (default 00) [31:24] (default 00) [23:16] (default 00) [15:8] (default 00) [7:0] (default 00) zl50410 data sheet 107 zarlink semiconductor inc. 12.3.8.4 rmac_mirror0 ? rmac mirror 0 cpu address 710 accessed by cpu (r/w) 12.3.8.5 rmac_mirror1 ? rmac mirror 1 cpu address 711 accessed by cpu (r/w) 12.3.9 (group 8 address) per port qos control 12.3.9.1 fcrn ? port 0~9 flooding control register i2c address h04c+n; cpu address:h800+n (n = port number) accessed by cpu and i2c (r/w) bits [2:0]: source port to be mirrored bit [3]: mirror path 0: receive 1: transmit bits [6:4]: destination port for mirrored traffic bit [7]: mirror enable bits [2:0]: source port to be mirrored bit [3]: mirror path 0: receive 1: transmit bits [6:4]: destination port for mirrored traffic bit [7]: mirror enable bits [3:0]: u2mr: unicast to multicast rate. un its in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic from port n. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disable this function, program u2mr to 0. (default = 0) bits [6:4]: time base for unicast to multicas t, multicast and broadc ast rate control of port n: (default = 000) 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 12.8 ms bit [7]: reserved zl50410 data sheet 108 zarlink semiconductor inc. 12.3.9.2 bmrcn - port 0~9 broadcast/multicast rate control i2c address h05e+n, cpu address:h820+n (n = port number) accessed by cpu and i2c (r/w) this broadcast and multicast rate defines for port n, t he number of packets allowed to be forwarded within a specified time. once the packet rate is reached, packets will be dropped. to turn off the rate limit, program the field to 0. time base is based on register fcr0 [6:4] 12.3.9.3 pr100_n ? port 0~7 reservation i2c address h06a+n, cpu address 840+n (n = port number) accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. (default 0x6) 12.3.9.4 pr100_cpu ? port cpu reservation i2c address h073, cpu address 848 accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. (default 0x6) 12.3.9.5 prg ? port gmac reservation i2c address h072, cpu address 849 accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. (default 0x24) 12.3.9.6 pth100_n ? port 0~7 threshold i2c address h0c2+n, cpu address 860+n (n = port number) accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. more than this numbe r used on a source port will trigger either random drop or flow control (default 0x3) 12.3.9.7 pth100_cpu ? port cpu threshold i2c address h0cb, cpu address 868 accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. more than this numbe r used on a source port will trigger either random drop or flow control (default 0x3) bits [3:0]: multicast rate control. number of mu lticast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcrn). (default 0). bits [7:4]: broadcast rate control. number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcrn). (default 0) zl50410 data sheet 109 zarlink semiconductor inc. 12.3.9.8 pthg ? port gmac threshold i2c address h0ca, cpu address 869 accessed by cpu and i2c (r/w) expressed in multiples of 16 granules. more than this numbe r used on a source port will trigger either random drop or flow control (default 0x12) 12.3.9.9 qosc00, qosc01 - classes byte limit port 0 accessed by cpu and i2c (r/w) ? qosc00 ? byte_l1 (i2c address h078, cpu address 880) ? qosc01 ? byte_l2 (i2c address h079, cpu address 881) multiple of 16 granules. the two numbers set the two leve l for wred on the high priority queue. when the queue size exceeds the l1 threshold, received frame will subjec t to x% (high drop) or y% (low drop) wred. when the queue size exceeds l2 threshold, receiv ed frame will either be filtered (h igh drop) or subject to z% wred. 12.3.9.10 qosc02, qosc15 - classes byte limit port 1-7 i2c address 07a-087, cpu address:h882-88f accessed by cpu and i2c (r/w) same as qosc00, qosc01 12.3.9.11 qosc16 - qosc21 - classes byte limit cpu port accessed by cpu and i 2 c (r/w): ? qosc16 ? byte_l11 level 1 for queue 1 (i 2 c address h088, cpu address 890) ? qosc17 ? byte_l21 level 2 for queue 1 (i 2 c address h089, cpu address 891) ? qosc18 ? byte_l12 level 1 for queue 2 (i 2 c address h08a, cpu address 892) ? qosc19 ? byte_l22 level 2 for queue 2 (i 2 c address h08b, cpu address 893) ? qosc20 ? byte_l13 level 1 for queue 3 (i 2 c address h08c, cpu address 894) ? qosc21 ? byte_l23 level 2 for queue 3 (i 2 c address h08d, cpu address 895) multiple of 16 granules. the two numbers set the two leve l for wred on the high priority queue. when the queue size exceeds the l1 threshold, received frame will subjec t to x% (high drop) or y% (low drop) wred. when the queue size exceeds l2 threshold, receiv ed frame will either be filtered (h igh drop) or subject to z% wred. 12.3.9.12 qosc22 - qosc27 - classes byte limit gmac port accessed by cpu and i2c (r/w) ? qosc22 ? byte_l11 level 1 for queue 1 (i2c address h08e, cpu address 896) ? qosc23 ? byte_l21 level 2 for queue 1 (i2c address h08f, cpu address 897) ? qosc24 ? byte_l12 level 1 for queue 2 (cpu address 898) ? qosc25 ? byte_l22 level 2 for queue 2 (cpu address 899) ? qosc26 ? byte_l13 level 1 for queue 3 (cpu address 89a) ? qosc27 ? byte_l23 level 2 for queue 3 (cpu address 89b) multiple of 16 granules. the two numbers set the two leve l for wred on the high priority queue. when the queue size exceeds the l1 threshold, received frame will subjec t to x% (high drop) or y% (low drop) wred. when the queue size exceeds l2 threshold, receiv ed frame will either be filtered (h igh drop) or subject to z% wred. zl50410 data sheet 110 zarlink semiconductor inc. 12.3.9.13 qosc28 - qosc31 - classes wfq credit for gmac accessed by cpu (r/w) w0 ? qosc28[5:0] ? credit_c00 (cpu address 89c) w1 ? qosc29[5:0] ? credit_c01 (cpu address 89d) w2 ? qosc30[5:0] ? credit_c02 (cpu address 89e) w3 ? qosc31[5:0] ? credit_c03 (cpu address 89f) qosc28 through qosc31 represents one set of wfq parame ters for gmac port. the gr anularity of the numbers is 1, and their sum must be 64. qosc 31 corresponds to w3 that is the hi ghest priority, and qosc27 corresponds to w0. default scheduling method will be strict priority across all queues. only when the bit 7 in the class is set, the queue will be scheduled as wfq. the credit number also wo rks as shaper credit if bit 6 is set. the queue with shaper enabled will be scheduled by strict priority when the token is available. the shaper setting override the ns setting. 12.3.9.14 qosc36 - qosc39 - shaper control port gmac accessed by cpu (r/w) w0 ? qosc36[7:0] ? token_limit_c00 (cpu address 8a4) w1 ? qosc37[7:0] ? token_limit_c01 (cpu address 8a5) w2 ? qosc38[7:0] ? token_limit_c02 (cpu address 8a6) w3 ? qosc39[7:0] ? token_limit_c03 (cpu address 8a7) qosc36 through qosc39 represents one set of token limi t on the shaper of gmac port. the granularity of the numbers is 64 bytes. the shaper is implemented as leaky bucket and the limi t here works as bucket size. since the hardware implementation can keep negative number, the limit can be as small as one and still can transmit oversized frame, as long as one byte token is available. 12.3.10 (group e address) system diagnostic note: device manufacturing test registers. 12.3.10.1 dtsrl ? test output selection cpu address e00 accessed by cpu (r/w) test group selection for testout[7:0]. 12.3.10.2 dtsrm ? test output selection cpu address e01 accessed by cpu (r/w) test group selection for testout[15:8]. bits [5:0]: class scheduling credit bit [6]: shaper enable bit [7]: not strict priority apply zl50410 data sheet 111 zarlink semiconductor inc. 12.3.10.3 testout0, testout1 ? testmux output [7:0], [15:8] cpu address e02, e03 accessed by cpu (ro) 12.3.10.4 mask0-mask4 ? timeout reset mask cpu address e10-e14 accessed by cpu (r/w) disable timeout reset on selected state machine status. see programming timeout reset application note, zlan-41, for more information. 12.3.10.5 bootstrap0 ? bootstrap3 cpu address e80-e83 accessed by cpu (ro) 12.3.10.6 prtfsmst0~9 cpu address e90+n accessed by cpu (ro) 31 23 15 0 bt3 bt2 bt1 bt0 bits [15:0]: bootstrap value from tstout[15:0]: bit [6:0]: tstout[6:0] bit [8:7]: invert of tstout[8:7] bit [9]: tstout[11] bit [10]: tstout[9] bit [11]: tstout[10] bit [14:12]: tstout[14:12] bit [15]: always 0 bits [23:16]: bootstrap value from m[7:0]_txen bit [16]: m0_txen bit [17]: m1_txen ... bit [23]: m7_txen bits [25:24]: bootstrap value from m9_txen, m9_txer bits [31:26]: reserved bit [0]: tx fsm not idle for 5 sec bit [1]: tx fifo control not idle for 5 sec bit [2]: rx sfd detection not idle for 5 sec bit [3]: rxinf not idle for 5 sec zl50410 data sheet 112 zarlink semiconductor inc. 12.3.10.7 prtqosst0-prtqosst7 cpu address ea0+n accessed by cpu (ro) 12.3.10.8 prtqosst8a, prtqosst8b (cpu port) cpu address ea8 ? ea9 accessed by cpu (ro) bit [4]: ptctl not idle for 5 sec bit [5]: reserved bit [6] lhb frame detected bit [7]: lhb receiving timeout bit [0]: source port reservation low bit [1]: no source port buffer left bit [2]: unicast congestion detected on best effort queue bit [3]: reserved bit [4]: high priority queue reach l1 wred level bit [5]: high priority queue reach l2 wred level bit [6]: low priority mc queue full bit [7]: high priority mc queue full 15 0 pqstb pqsta bit [0]: source port reservation low bit [1]: no source port buffer left bit [2]: unicast congestion detected on best effort queue bit [3]: reserved bit [4]: priority queue 1 reach l1 wred level bit [5]: priority queue 1 reach l2 wred level bit [6]: priority queue 2 reach l1 wred level bit [7]: priority queue 2 reach l2 wred level bit [8]: priority queue 3 reach l1 wred level zl50410 data sheet 113 zarlink semiconductor inc. 12.3.10.9 prtqosst9a, prtqosst9b (gmac port) cpu address eaa ? eab accessed by cpu (ro) bit [9]: priority queue 3 reach l2 wred level bit [10]: priority 0 mc queue full bit [11]: priority 1 mc queue full bit [12]: priority 2 mc queue full bit [13]: priority 3 mc queue full bits [15:14]: reserved 15 0 pqstb pqsta bit [0]: source port reservation low bit [1]: no source port buffer left bit [2]: unicast congestion detected on best effort queue bit [3]: reserved bit [4]: priority queue 1 reach l1 wred level bit [5]: priority queue 1 reach l2 wred level bit [6]: priority queue 2 reach l1 wred level bit [7]: priority queue 2 reach l2 wred level bit [8]: priority queue 3 reach l1 wred level bit [9]: priority queue 3 reach l2 wred level bit [10]: priority 0 mc queue full bit [11]: priority 1 mc queue full bit [12]: priority 2 mc queue full bit [13]: priority 3 mc queue full bits [15:14]: reserved zl50410 data sheet 114 zarlink semiconductor inc. 12.3.10.10 classqosst cpu address eac accessed by cpu (ro) 12.3.10.11 prtintctr cpu address ead accessed by cpu (r/w) 12.3.10.12 qmctrl0~9 cpu address eb0+n accessed by cpu (r/w) bit [0]: no share buffer bit [1]: no class 1 buffer bit [2]: no class 2 buffer bit [3]: no class 3 buffer bits [7:4]: reserved bit [0]: interrupt when source buffer low bit [1]: interrupt when no source buffer bit [2]: interrupt when uc congest bit [3]: interrupt when l1 wred level bit [4]: interrupt when l2 wred level bit [5]: interrupt when mc queue full bit [6]: interrupt when lhb timeout bit [7]: interrupt when no class buffer bit [0]: suspend port sc heduling (no departure) bit [1]: reset queue bits [4:2]: reserved bit [5]: force out mac control frame bit [6]: force out xoff flow control frame bit [7]: force out xon flow control frame zl50410 data sheet 115 zarlink semiconductor inc. 12.3.10.13 qctrl cpu address eba accessed by cpu (r/w) 12.3.10.14 bmbistr0, bmbistr1 cpu address ebb, ebc accessed by cpu (ro) 12.3.10.15 bmcontrol cpu address ebd accessed by cpu (r/w) bit [0]: stop qm fsm at idle bit [1]: stop mcq fsm at idle bit [2]: stop new granule grant to any source bit [3]: stop release granule from any source bits [7:4]: reserved bits [3:0]: block memory redundancy control 0: use hardware detected value all others: overwrite the hardware detected memory swap map bits [7:4]: reserved zl50410 data sheet 116 zarlink semiconductor inc. 12.3.10.16 buff_rst cpu address ec0 accessed by cpu (r/w) if cpu wants to reset pools again, cpu has to clear bit 5 and then set bit 5. note : before cpu doing so, cpu should set qctrl (cpu address eba) bit 2 and bit 3 to one. after reset the pools, cpu shall reprogram free granule link list (cpu address ec1, ec2, ec3, ec4, ec5, ec6). then clear qctrl (eba). 12.3.10.17 fcb_head_ptr0, fcb_head_ptr1 cpu address ec1 accessed by cpu (r/w) cpu address ec2 accessed by cpu (r/w) if cpu wants to write again, cpu has to clear bit 15 and then set bit 15. bits [3:0] assign a value that the pool to be reset 0: port 0 pool 1: port 1 pool 2: port 2 pool 3: port 3 pool 4: port 4 pool 5: port 5 pool 6: port 6 pool 7: port 7 pool 8: port gmac pool 9: shared pool 10: class 1 pool 11: class 2 pool 12: class 3 pool 13: multicast pool 14: cpu pool 15: reserved bit [4] if this bit is 1, then all the pools are assigned bit [5] set 1 to reset the pools that are assigned bits [7:6] reserved bits [7:0] fcb_head_ptr[7:0]. the head pointer of free granule link t hat cpu assigns. bits [6:0] fcb_head_ptr[14:8]. the head pointer of free granule link that cpu assigns. bit [7] set 1 to write zl50410 data sheet 117 zarlink semiconductor inc. 12.3.10.18 fcb_tail_ptr0, fcb_tail_ptr1 cpu address ec3 accessed by cpu (r/w) cpu address ec4 accessed by cpu (r/w) if cpu wants to write again, cpu has to clear bit 15 and then set bit 15. 12.3.10.19 fcb_num0, fcb_num1 cpu address ec5 accessed by cpu (r/w) cpu address ec6 accessed by cpu (r/w) if cpu wants to write again, cpu has to clear bit 15 and then set bit 15. note : there are two ways to reprogram the free granules. 1. cpu links all the granules: cpu writes memory directly , at last write head pointer (address ec1, ec2), tail pointer (address ec3, ec4) and granule number (address ec5, ec6). 2. cpu tells buffer manager to link: cpu clear head pointer (address ec1, ec2), clear tail pointer (address ec3, ec4), then write granule number that tells bu ffer manager to link (address ec5, ec6). 12.3.10.20 bm_rlsff_ctrl cpu address ec7 accessed by cpu (r/w) the information of bm release fifo is relocated to registers bm_rlsff_in fo (address ecd, ecc, ecb, eca, ec9 and ec8). if the fifo is not empty, cpu can read out the next by setting the bit 0. read only happens when bit 0 is changing from 0 to 1. bits [7:0] fcb_tail_ptr[7:0]. the tail point er of free granule link that cpu assigns. bits [6:0] fcb_tail_ptr[14:8]. the tail point er of free granule lin k that cpu assigns. bit [7] set 1 to write bits [7:0] fcb_number[7:0]. the total number of granules that cpu assigns. bits [6:0] fcb_number[14:8]. the total number of granules that cpu assigns. bit [7] set 1 to write bit [0] read bm release fifo. bits [7:1] reserved zl50410 data sheet 118 zarlink semiconductor inc. 12.3.10.21 bm_rslff_info[5:0] cpu address ec8 accessed by cpu (ro) cpu address ec9 accessed by cpu (ro) cpu address eca accessed by cpu (ro) cpu address ecb accessed by cpu (ro) cpu address ecc accessed by cpu (ro) cpu address ecd accessed by cpu (ro) bits [7:0] rls_head_ptr[7:0]. bits [6:0] rls_head_ptr[14:8]. bit [7] rls_tail_ptr[0] bits [7:0] rls_tail_ptr[8:1] bits [5:0] rls_tail_ptr[14:9] bits [7:6] rls_count[1:0] bits [4:0] rls_count[6:2] bit [5] if 1, then it is multicast packet. bits [7:6] rls_src_port[1:0[ bits [1:0] rls_src_port[3:2] bits [3:2] class[1:0] bit [4] this release request is from qm directly. bits [7:5] entries count in rel ease fifo, 0 means fifo is empty zl50410 data sheet 119 zarlink semiconductor inc. 12.3.11 (group f address) cpu access group 12.3.11.1 gcr - global control register cpu address: hf00 accessed by cpu (r/w) 12.3.11.2 dcr - device status and signature register cpu address: hf01 accessed by cpu (ro) bit [0]: store configuration (default = 0) write ?1? followed by ?0? to store configuration into external eeprom bit [1]: store configuration and reset (default = 0) write ?1? to store configuration in to external eeprom and reset chip bit [2]: start bist (default = 0) write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit [3]: soft reset (default = 0) write ?1? to reset chip bit [4]: initialization completed (default = 0) this bit is reserv ed in unmanaged mode. in managed mode, the cpu writes this bit with ?1? to indicate initialization is completed and ready to forward packets . the ?0' to '1' transition will toggle tstout[2] from low to high. bits [7:5]: reserved bit [0]: 1: busy writin g configuration to i2c 0: not busy (not writin g configuration to i2c) bit [1]: 1: busy reading configuration from i2c 0: not busy (not reading configuration from i2c) bit [2]: 1: bist in progress 0: bist not running bit [3]: 1: ram error 0: ram ok bits [5:4]: device signature 11: zl50410 device bits [7:6]: revision 00: initial silicon 01: second silicon 10: third silicon zl50410 data sheet 120 zarlink semiconductor inc. 12.3.11.3 dcr1 - device status register 1 cpu address: hf02 accessed by cpu (ro) 12.3.11.4 dpst ? device port status register cpu address:hf03 accessed by cpu (r/w) 12.3.11.5 dtst ? data read back register cpu address: hf04 accessed by cpu (ro) this register provides various internal information as selected in dpst bit [4:0]. refer to the phy port control application note, zlan-37. bits [6:0] reserved bit [7] chip initialization completed bits [4:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) - 5?b00000 - port 0 operating mode and negotiation status - 5?b00001 - port 1 operating mode and negotiation status - 5?b00010 - port 2 operating mode and negotiation status - 5?b00011 - port 3 operating mode and negotiation status - 5?b00100 - port 4 operating mode and negotiation status - 5?b00101 - port 5 operating mode and negotiation status - 5?b00110 - port 6 operating mode and negotiation status - 5?b00111 - port 7 operating mode and negotiation status - 5?b01000 - port cpu operating mode and negotiation status - 5?b01001 - port gmac operating mode and negotiation status bits [7:5]: reserved bit [0] flow control enable 1: flow control 0: no flow control bit [1] full duplex port 1: full duplex 0: half duplex bit [2] fast ethernet port (if bit [5] not set) 1: fe port bit [3] link is down 1: link down 0: link up zl50410 data sheet 121 zarlink semiconductor inc. 12.3.11.6 da ? dead or alive register cpu address: hfff accessed by cpu (ro) always return 8?h da . indicate the cpu interface or serial port connection is good. bit [4] auto negotiation disabled 1: disable 0: enable bit [5] gigabit ethernet port 1: ge port bit [6] reserved bit [7] module detected (for hot swap purpose) 0: no module 1: module detected note: if module detect feature is disabl ed (bootstrap tstout[9]=?0?), this bit will always be ?1?. bits [7:0] always return da zl50410 data sheet 122 zarlink semiconductor inc. 13.0 characteristics and timing 13.1 absolute maximum ratings storage temperature -65 c to +150 c operating temperature -40 c to +85 c maximum junction temperature +125 c supply voltage v cc with respect to v ss +2.95 v to +3.65 v supply voltage v dd with respect to v ss +1.60 v to +2.00 v voltage on 5 v tolerant input pins -0.5 v to (v cc + 2.5 v) voltage on other pins -0.5 v to (v dd + 0.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functi onality at or above these limits is not implied. 13.2 dc electrical characteristics v cc = 3.3 v +/- 10% t ambient = -40 c to +85 c v dd = 1.8 v +/- 5% zl50410 data sheet 123 zarlink semiconductor inc. 13.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation (sclk) 100 100 mhz i cc v cc supply current ? @ 100 mhz (full line rate) 105 ma i dd v dd supply current ? @ 100 mhz (full line rate) 350 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih input high voltage (ttl 5 v tolerant) 2.0 v cc + 2.0 v v il input low voltage (ttl 5 v tolerant) 0.8 v i il input leakage current (0.1 v < v in < v cc ) (all pins except those with internal pull-up/pull-down resistors) 10 a i ol output leakage current (0.1 v < v out < v cc ) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 24.3 c/w ja thermal resistance with 1 m/s air flow 20.0 c/w ja thermal resistance with 2 m/s air flow 18.1 c/w jc thermal resistance between junction and case 4.6 c/w zl50410 data sheet 124 zarlink semiconductor inc. 13.4 ac characteristics and timing 13.4.1 typical reset & bootstrap timing diagram figure 13 - typical reset & bootstrap timing diagram symbol parameter min. typ. note: r1 delay until resetout# is tri-stated 10 ns resetout# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of resin# r3 resetout# assertion 2 ms resetout# tri-stated resin# r1 r2 r3 bootstrap pins inputs outputs outputs zl50410 data sheet 125 zarlink semiconductor inc. 13.4.2 typical cpu timing diagram for a cpu write cycle figure 14 - typical cpu timing diagram for a cpu write cycle description (sclk=100 mhz) (sclk=50 mhz) refer to figure 14 write cycle symbol min. max. min. max. write set up time t ws 10 10 p_a and p_cs# to falling edge of p_we# write active time t wa 20 40 at least 2 sclk cycles write hold time t wh 2 2 p_a and p_cs# to rising edge of p_we# write recovery time t wr 30 60 at least 3 sclk cycles data set up time t ds 10 10 p_data to falling edge of p_we# data hold time t dh 2 2 p_data to rising edge of p_we# p_cs# p_we# p_data (to dev ice) p_a[2:0] t wr recov ery tim e hold time addr0 t ws t wa activ e tim e set up time data1 data0 addr1 t wh t ws t wa activ e tim e t wh t dh t dh t ds t ds zl50410 data sheet 126 zarlink semiconductor inc. 13.4.3 typical cpu timing diagram for a cpu read cycle figure 15 - typical cpu timing diagram for a cpu read cycle table 14 - ac characteristics - cpu read cycle description (sclk=100 mhz) (sclk=50 mhz) refer to figure 15 read cycle symbol min. max. min. max. read set up time t rs 10 10 p_a and p_cs# to falling edge of p_rd# read active time t ra 20 40 at least 2 sclk cycles read hold time t rh 2 2 p_a and p_cs# to rising edge of p_rd# read recovery time t rr 30 60 at least 3 sclk cycles data valid time t dv 12 12 p_data to falling edge of p_rd# data invalid time t di 10 10 p_data to rising edge of p_rd# p_cs# p_rd# p_data (to cpu) p_a[2:0] t rr recov ery tim e inv alid time addr0 t rs t dv t ra activ e tim e valid tim e data1 data0 t di addr1 t rh t rs t ra activ e tim e t rh t di t dv zl50410 data sheet 127 zarlink semiconductor inc. 13.4.4 reduced medi a independent interface figure 16 - ac characteristics ? reduc ed media independent interface (tx) figure 17 - ac characteristics ? redu ced media independent interface (rx) symbol parameter m_clk=50 mhz note: min. (ns) max. (ns) m2 m[7:0]_rxd[1:0] input setup time 4 m3 m[7:0]_rxd[1:0] input hold time 2 m4 m[7:0]_crs_dv input setup time 4 m5 m[7:0]_crs_dv input hold time 3 m6 m[7:0]_txen output delay time 2 11 c l = 20 pf m7 m[7:0]_txd[1:0] output delay time 2 11 c l = 20 pf m6-min m6-max m7-min m7-max m_clk mn_txen mn_txd[1:0] m2 m_clk mn_rxd mn_crs_dv m3 m4 m5 zl50410 data sheet 128 zarlink semiconductor inc. 13.4.5 media independent interface figure 18 - ac characteristics ? media independent interface (tx) figure 19 - ac characteristics ? media independent interface (rx) symbol parameter 25 mhz note: min. (ns) max. (ns) mm2 m[9,7:0]_rxd[3:0] input setup time 4 mm2 m[8]_rxd[3:0] input setup time 10 cpu mii interface mm3 mn_rxd[3:0] input hold time 2 mm4 m[9,7:0]_crs_dv input setup time 4 mm4 m[8]_crs_dv input setup time 10 cpu mii interface mm5 mn_crs_dv input hold time 2 mm6 mn_txen output delay time 2 14 c l = 20 pf mm7 mn_txd[3:0] output delay time 2 14 c l = 20 pf mm6-min mm6-max mm7-min mm7-max mn_txclk mn_txen mn _txd[3:0] mm2 mn_rxclk mn_rxd[3:0] mn_crs_dv mm 3 mm4 mm 5 zl50410 data sheet 129 zarlink semiconductor inc. 13.4.6 general purpose serial interface (7-wire) figure 20 - ac characteristics ? general purpose serial interface (tx) figure 21 - ac characteristics ? ge neral purpose serial interface (rx) symbol parameter 10 mhz note: min. (ns) max. (ns) sm2 m[7:0]_rxd input setup time 4 sm3 m[7:0]_rxd input hold time 2 sm4 m[7:0]_crs_dv input setup time 4 sm5 m[7:0]_crs_dv input hold time 2 sm6 m[7:0]_txen output delay time 2 14 c l = 20 pf sm7 m[7:0]_txd output delay time 2 14 c l = 20 pf sm6-min sm6-max sm7-min sm7-max mn_ txclk mn_txen mn_txd sm2 mn_rxclk mn_rxd mn_crs_dv sm3 sm4 sm5 zl50410 data sheet 130 zarlink semiconductor inc. 13.4.7 gigabit media independent interface figure 22 - ac characteristics- gigabi t media independent interface (tx) figure 23 - ac characteristics ? giga bit media independent interface (rx) g12-min g12-max g13-min g13-max g14-min g14-max m9_txclk m9_txd [7:0] m9_txen m9_txer g1 g2 g7 g8 g5 g6 g3 g4 m9_rxd[7:0] m9_rxdv m9_rxer m9_rx_crs m9_rxclk m9_rxclk m9_rxd[7:0] m9_rxdv m9_rxer m9_rx_crs zl50410 data sheet 131 zarlink semiconductor inc. symbol parameter 125 mhz note: min. (ns) max. (ns) g1 m9_rxd[7:0] input setup times 2 g2 m9_rxd[7:0] input hold times 1 g3 m9_rxdv input setup times 2 g4 m9_rxdv input hold times 1 g5 m9_rxer input setup times 2 g6 m9_rxer input hold times 1 g7 m9_crs input setup times 2 g8 m9_crs input hold times 1 g12 m9_txd[7:0] output delay times 1 6 c l = 20 pf g13 m9_txen output delay times 1 6.5 c l = 20 pf g14 m9_txer output delay times 1 6 c l = 20 pf zl50410 data sheet 132 zarlink semiconductor inc. 13.4.8 mdio input setup and hold timing figure 24 - mdio input setup and hold timing figure 25 - mdio output delay timing symbol parameter mdc=500 khz note: min. (ns) max. (ns) d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50 pf mdc d1 d2 mdio d3-min d3-max mdc mdio zl50410 data sheet 133 zarlink semiconductor inc. 13.4.9 i2c input setup timing figure 26 - i2c input setup timing figure 27 - i2c output delay timing symbol parameter scl=50 khz note: min. (ns) max. (ns) s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 4 usec 6 usec c l = 30 pf * open drain output. low to high transistor is controlled by external pullup resistor. s1 s2 scl sda s3-min s3-max scl sda zl50410 data sheet 134 zarlink semiconductor inc. 13.4.10 serial interface setup timing figure 28 - serial interface setup timing figure 29 - serial interface output delay timing symbol parameter min. (ns) max. (ns) note: d1 datain setup time 20 d2 datain hold time 3 s debounce on 20 ns debounce off d3 dataout output delay time 1 50 c l = 100 pf d4 strobe low time 5 s debounce on 50 ns debounce off d5 strobe high time 5 s debounce on 50 ns debounce off d4 d5 d2 d1 d2 d1 strobe datain d3-min d3-max strobe dataout zl50410 data sheet 135 zarlink semiconductor inc. 13.4.11 jtag (ieee 1149.1-2001) figure 30 - jtag timing diagram symbol parameter min. typ. max. units note: tck frequency of operation 0 10 50 mhz tck cycle time 20 ns tck clock pulse width 10 ns trst# assert time 20 - ns trst is an asynchronous signal j1 tms, tdi data setup time 3 ns j2 tms, tdi data hold time 7 ns j3 tck to tdo data valid 0 15 ns tms, tdi tck j1 j3-max tdo j2 j3-min zl50410 data sheet 136 zarlink semiconductor inc. 14.0 document history 14.1 july 2003 ? initial release 14.2 november 2003 ? clarified ip multicast support is up to 4 k gr oups, as it wasn?t mentioned in the data sheets ? updated ball signal description table: ? clarified the ball signal i/o description for mn_t xclk & mn_rxclk showing these signals are either inputs or outputs ? clarified that m9_mtxclk is an input only ? updated section 1.4 on page 17 to indicate operation of the internal pull-up/dow n resistors in different modes ? clarified section 10.1.3 on page 50 on usage of gref_clk ? clarified pvmode register bit description for bits [2] & [5] ? updated ecr4pn register description as port 9 (uplin k) operates differently than the rmac ports for mii bi-directional clocking (bits [1:0]) ?i 2 c address mapping was corrected for qoscn registers ? added maximum junction temperature to section 13.1 on page 122 ? updated i/o voltage levels to use ttl spec values rather than % of vcc 14.3 february 2004 ? added the following to the feature list: ? 4 k jumbo frames ? ieee 802.3ad support ? reverse mii/gpsi ? added section on phy addresses ? clarified that they are hard-coded ? fixed error in ds on sending ethernet fr ames via 8/16-bit or serial interface. ? the status bytes is sent before the frame, for both tx and rx ? added more cross-references to available appnotes ? added section on stacked vlan (q-in-q) and ip multic ast switching since they weren?t really discussed in the ds ? added more clock descriptions to ?clocks? on page 50 ? int_mask and intp_mask registers should stat e that the default r egister value is 0x00 14.4 august 2004 ? added errata list to document ? added section on scl clock generation ? interrupt register was incorrectly iden tified as read only, should be read/write ? clarified that only bit [7 ] is not self-clearing ? updated cpu timing diagr ams to clarify timing 14.5 november 2004 ? added section ?default switch configurati on and initialization sequence? on page 21 ? added private vlan edge (protected ports), force vlan tag out, and unknown ip multicast filtering support ? updated cpu timing diagram s to clarify p_a timing c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code previous package codes side view b top view bottom view 0.53 ref a2 208 1.00 n e e b d 16.90 0.40 16.90 17.10 0.60 17.10 a a1 0.30 min 0.50 max 1 213730 14nov02 1.40 dimension conforms to jedec mo-192 www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
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